Correlated Double Sampling Circuit with Feedback Gain Control
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Solution Overview
Problem
Conventional CMOS image sensors face challenges in adjusting image capture sensitivity due to mismatch issues in programmable gain amplifier circuits, which are area-intensive and require additional components, complicating the integration of correlated double sampling and programmable gain amplification operations.
Innovation Solution
A correlated double sampling circuit that performs both CDS and PGA operations, incorporating a sampling circuit, an offset correction circuit, and a feedback unit to amplify and output signals, allowing for adjustable capacitance ratios and automatic offset voltage correction, thereby eliminating the need for separate PGA circuits and reducing overall area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional PGA circuit with multiple capacitors is used for sensitivity adjustment, then programmable gain amplification can be achieved, but capacitor mismatch occurs and circuit area increases
Solution Approach 1:
The patent merges the CDS circuit and PGA circuit into a single integrated structure. The CDS circuit performs correlated double sampling to eliminate noise, while the PGA circuit simultaneously provides programmable gain amplification through capacitor switching. This integration eliminates the need for separate capacitor arrays, reducing both area and mismatch issues while maintaining sensitivity adjustment capability.
Solution Approach 2:
The CDS circuit is designed to perform multiple functions: it executes correlated double sampling for noise reduction and simultaneously provides programmable gain amplification through its capacitor network. This multi-functionality eliminates the need for dedicated PGA components, reducing overall circuit area and component count while maintaining adaptability for sensitivity adjustment.
2Adaptability or versatility
If a separate PGA circuit is added to each column for sensitivity adjustment, then programmable gain amplification is achieved, but the total area of the CIS increases
Solution Approach 1:
The patent merges the CDS circuit and PGA circuit into a single integrated structure. The CDS circuit performs correlated double sampling to eliminate noise, while the PGA circuit simultaneously provides programmable gain amplification through capacitor switching. This integration eliminates the need for separate capacitor arrays, reducing both area and mismatch issues while maintaining sensitivity adjustment capability.
Solution Approach 2:
The CDS circuit is designed to perform multiple functions: it executes correlated double sampling for noise reduction and simultaneously provides programmable gain amplification through its capacitor network. This multi-functionality eliminates the need for dedicated PGA components, reducing overall circuit area and component count while maintaining adaptability for sensitivity adjustment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient sensitivity adjustment and amplification of signals within the CMOS image sensor without increasing the total area, ensuring high sensitivity standards and automatic offset voltage cancellation.
Implementation Method 1
a sampling circuit configured to perform a CDS on a reset signal and an image signal respectively during a CDS phase and to output a difference between a correlated double sampled reset signal and a correlated double sampled image signal
Implementation Method 2
a feedback unit configured to feed back the difference output from the sampling circuit to an input of the sampling circuit during a PGA phase
Implementation Method 3
The sampling circuit is configured to accumulate or amplify and output the difference fed back during the PGA phase by N times
Data Source
AI summary
A correlated double sampling (CDS) circuit is provided. The CDS circuit is configured to perform a CDS on a reset signal and an image signal during a CDS phase respectively. The CDS circuit includes a sampling circuit configured to output a difference between a correlated double sampled reset signal and a correlated double sampled image signal, and a feedback unit configured to feedback the difference output from the sampling circuit during a PGA phase to an input of the sampling circuit.


