Differential CDS Switched-Capacitor Integrator With Leakage Compensation
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Solution Overview
Problem
Existing switched-capacitor gain circuits face accuracy limitations due to flicker noise, finite amplifier gain, and DC offsets, while correlated double sampling (CDS) techniques, used to improve accuracy, are hindered by parasitic capacitances that result in integrator leakage, limiting Analog-to-Digital Converter (ADC) resolution to 16 bits.
Innovation Solution
A differential CDS switched capacitor integrator circuit is designed with dummy capacitive elements that cross-couple capacitance between inputs and outputs of the amplifier, compensating for parasitic capacitance of integration switches, thereby counteracting charge loss and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If correlated double sampling (CDS) is used to compensate for offset and improve accuracy, then measurement precision is improved, but parasitic capacitances cause integrator leakage that limits ADC resolution
Solution Approach 1:
A compensation capacitor is introduced as an intermediary element to capture and store the charge lost to parasitic capacitance during the integration process. This compensation capacitor acts as a mediator that transfers the leaked charge back to the integration capacitor, thereby compensating for the integrator leakage and enabling higher ADC resolution beyond the 16-bit limitation.
2Device complexity
If simple CDS sampling scheme is used, then device complexity is reduced, but integrator leakage limits resolution to 16 bits
Solution Approach 1:
The invention changes the electrical parameters of the integration system by adding a compensation capacitor with a specific capacitance value. This parameter change enables the system to track and compensate for charge loss dynamically, transforming the fixed 16-bit resolution limitation into a variable resolution system that can achieve higher precision without fundamentally redesigning the entire CDS architecture.
3Measurement precision
If parasitic capacitance of integration switches is present, then charge redistribution occurs causing signal loss, but adding compensation components increases circuit complexity
Solution Approach 1:
The compensation capacitor serves as a minimal intermediary component that specifically addresses the charge redistribution problem caused by parasitic capacitance. By introducing this single compensation element, the circuit recovers lost signal charge without requiring multiple complex compensation networks or redesigning the switch architecture, thus achieving signal accuracy improvement with minimal complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively compensates for parasitic capacitance, enhancing the accuracy and resolution of ADCs beyond 16 bits by canceling out charge sharing effects, leading to improved linearity and precision in analog signal conversion.
Implementation Method 1
The CDS integrator circuit 100 is sensitive to parasitic capacitances across the integration switches 102, 104, 106, and 108
Implementation Method 2
Due to the charge redistribution (e.g., from C2 to the parasitic capacitance of switch 102), a portion of the integrated signal is therefore lost
Data Source
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AI summary
Methods and systems for a differential correlated double sampling (CDS) switched capacitor integrator circuit. The circuit includes a differential amplifier that has a differential input and a differential output. There is a first feedback path between the negative output node and the positive input node, and a second feedback path between the positive output node and the negative input node. Each feedback path includes an integration capacitor and at least one switch that has a parasitic capacitance. A first capacitive element is coupled between the negative input node and the negative output node, and a second capacitive element is coupled between the positive input node and the positive output node. Each capacitive element is configured to cancel the parasitic capacitance of its corresponding feedback path.