CDS Integrating Circuit With Level Shifting for Leakage Reduction

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Solution Overview

Problem

Integrator leakage in CDS integrators due to limited gain of Opamps at advanced process nodes, which affects the effectiveness of offset voltage cancellation.

Innovation Solution

A CDS integrating circuit with a level shifting module that increases loop gain by sampling and shifting the Opamp output voltage towards a common-mode voltage, using Correlated Level Shifting (CLS) technique, enhancing the CDS integration module's ability to cancel offset voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If CDS integrator is used to reduce offset voltage and improve SNR, then signal quality is improved, but integrator leakage occurs due to limited Opamp gain at advanced process nodes

Engineering Contradiction:
ImproveSignal to Noise RatioVSAvoidIntegrator leakage
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the Opamp output voltage is sampled and fed back through the level shifting capacitor to adjust the output. This feedback loop allows the system to compensate for the limited Opamp gain by continuously monitoring and correcting the output voltage, thereby reducing integrator leakage while maintaining the CDS integrator's ability to improve SNR

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The level shifting capacitor acts as an intermediary element between the Opamp output and the CDS integration module output. It mediates the voltage level by sampling the Opamp output and shifting it towards the common-mode voltage, effectively bridging the gap caused by limited Opamp gain and preventing integrator leakage

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If Opamp gain is increased to improve offset voltage cancellation, then integrator performance is improved, but device complexity and power consumption increase at advanced process nodes

Engineering Contradiction:
ImproveOffset voltage cancellationVSAvoidOpamp design complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the offset voltage cancellation function into two parts: the primary CDS integration module and the auxiliary level shifting module. This segmentation allows the system to achieve improved offset voltage cancellation without requiring a single complex high-gain Opamp, thereby reducing device complexity while maintaining effectiveness

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The level shifting capacitor serves as an intermediary that enhances the offset voltage cancellation capability without requiring increased Opamp gain. By introducing this intermediate voltage shifting stage, the system achieves better offset cancellation performance without increasing the complexity of the main Opamp design

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12549175B2Correlated double sampling integrating circuit and data converter
Publication Date: 2026.02.10 SHEN AN MICRO CO LTD
  • US12549175B2 patent drawing
  • US12549175B2 patent drawing
  • US12549175B2 patent drawing

AI summary

A Correlated Double Sampling (CDS) integrating circuit and a data converter, the CDS circuit includes a CDS integration module and a level shifting module. The CDS integration module is configured to sample a first input signal and an Operational Amplifier (Opamp) input offset voltage to a sampling capacitor during a first phase; and sample a second input signal and the Opamp input offset voltage to the sampling capacitor during a second phase, and transfer a charge difference generated on the sampling capacitor to an integrating capacitor. The level shifting module is configured to sample an output signal and a common-mode voltage to a level shifting capacitor during a first stage of the first phase and the second phase, and shift a potential of an Opamp output voltage towards the common-mode voltage through the level shifting capacitor in a second stage of the second phase.