Clock Data Recovery System for Serdes Using Adaptive DFE
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Solution Overview
Problem
Conventional serializer/deserializer (Serdes) systems face challenges in high-speed data transmission due to signal distortion and inter-symbol interference (ISI) caused by channel characteristics, which degrade signal quality and increase bit error rates, especially at high data rates like 16 Gbps.
Innovation Solution
The proposed clock data recovery system incorporates a continuous time linear equalizer, adder, error slicers, a data slicer, an adaptive filter, and a decision feedback equalizer to generate and adjust clock signals, using adaptive filtering and feedback mechanisms to suppress post-cursors and reduce ISI, thereby stabilizing the system and improving signal reconstruction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional clock data recovery systems operate at double data rate to oversample the signal, then sampling accuracy improves, but system complexity and power consumption increase significantly
Solution Approach 1:
The patent transitions from a static double-data-rate sampling architecture to a dynamic baud-rate sampling architecture where the clock signal frequency adapts to match the data rate. This dynamic adjustment allows the system to maintain sampling accuracy while reducing operational complexity by eliminating the need for dual-frequency clock generation and associated phase alignment mechanisms.
Solution Approach 2:
The system changes the key parameter of clock signal frequency from a fixed double-data-rate value to a variable baud-rate value that matches the data transmission rate. This parameter change fundamentally simplifies the sampling architecture while maintaining the necessary sampling accuracy for reliable data recovery.
2Reliability
If equalization mechanisms with multiple taps are used to compensate channel effects, then signal quality improves, but device complexity increases
Solution Approach 1:
The patent divides the equalization function into two distinct segments: a continuous-time linear equalizer (CTLE) that operates in the analog domain to handle high-frequency signal degradation, and a decision feedback equalizer (DFE) that operates in the digital domain to eliminate inter-symbol interference. This segmentation allows each equalizer type to be optimized for its specific function, improving overall signal quality while managing complexity through functional specialization.
Solution Approach 2:
The patent introduces an adaptive filter as an intermediary component that dynamically adjusts the coefficients of both the CTLE and DFE based on real-time signal conditions. This adaptive intermediary optimizes the performance of the equalization system without requiring manual tuning or complex fixed-coefficient designs, thereby improving signal quality while keeping the system adaptable to varying channel conditions.
3Speed
If high data rates are transmitted through low-pass channels, then transmission speed improves, but signal distortion and inter-symbol interference increase
Solution Approach 1:
The patent applies pre-emphasis filtering at the transmitter side as a preliminary action to compensate for the low-pass characteristics of the channel before signal transmission. This pre-emphasis boosts the high-frequency components that would otherwise be attenuated by the channel, proactively counteracting the expected signal degradation and enabling high-speed transmission with reduced distortion.
Solution Approach 2:
The patent implements a decision feedback equalizer that uses feedback from previously decided data symbols to cancel out inter-symbol interference in the current symbol. This feedback mechanism continuously adapts to channel conditions and actively compensates for signal distortion, maintaining high signal quality even at elevated data rates where distortion would normally be problematic.
Data Source
AI summary
A clock data recovery system is provided. A CTLE generates a first equalized signal. An adder superposes the first equalized signal and a feedback equalization signal and generates a superposed signal. A first error slicer slices the superposed signal according to a clock signal and a reference voltage and generates a first error signal. A second error slicer slices the superposed signal according to the clock signal and a second slicing voltage. A data slicer slices the superposed signal according to the clock signal and a third slicing voltage and generates a data signal. A CDR circuit generates the clock signal. An adaptive filter receives the data signal and the first error signal, and generates the reference voltage and a DFE coefficient set. A DFE receives the data signal and the DFE coefficient set, and generates the feedback equalization signal.