Correlated Double Sub-Sampling Circuit for APS Pixel Noise Reduction

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Solution Overview

Problem

Current CMOS image sensors face challenges in efficiently subsampling pixels while maintaining high signal-to-noise ratio and reducing power consumption, as existing methods require multiple CDS subtractions and consume additional electrical power for memory and processing.

Innovation Solution

The implementation of Correlated Double Sub-Sampling (CDSS) method, which averages and subtracts reset and image signal charges from multiple pixels in the analog domain, reducing the need for individual pixel CDS operations and enhancing power efficiency by performing subsampling in three stages: averaging reset and signal voltages in the column and row directions, followed by a single analog subtraction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If individual CDS operations are performed for each pixel, then signal-to-noise ratio is improved, but power consumption increases

Engineering Contradiction:
Improvesignal-to-noise ratioVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent merges CDS operations by accumulating reset charges and signal charges from multiple pixels into common capacitors before performing subtraction. This combines multiple individual CDS operations into a single operation, reducing power consumption while maintaining signal-to-noise ratio through the correlated subtraction of accumulated charges.

Inventive Principle:
Principle #5Merging (Combining)

2Measurement precision

If multiple CDS subtractions are performed, then noise correction is improved, but device complexity increases

Engineering Contradiction:
Improvenoise correctionVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges multiple CDS subtraction operations into a single subtraction by accumulating charges from multiple pixels in shared capacitors. This reduces circuit complexity by eliminating the need for separate subtractor circuits for each pixel while maintaining effective noise correction through the correlated double sampling of accumulated charges.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements multi-functional capacitors that serve dual purposes: accumulating charges from multiple pixels and performing the CDS subtraction operation. This universal approach allows the same hardware components to handle both charge accumulation and noise correction functions, reducing overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If subsampling is performed in digital domain, then processing flexibility is improved, but power consumption increases

Engineering Contradiction:
Improveprocessing flexibilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent replaces digital domain subsampling operations with analog domain charge accumulation and subtraction. By performing CDS operations on accumulated charges before digital conversion, the system achieves subsampling functionality in the analog domain, reducing the computational burden and power consumption associated with digital processing while maintaining flexibility through programmable accumulation periods.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS7554584B2Method and circuit for performing correlated double sub-sampling (CDSS) of pixels in an active pixel sensor (APS) array
Publication Date: 2009.06.30 SAMSUNG ELECTRONICS CO LTD
  • US7554584B2 patent drawing
  • US7554584B2 patent drawing
  • US7554584B2 patent drawing

AI summary

A method and circuit for performing Correlated Double Sub-Sampling (CDSS) of pixels in an active pixel sensor (APS) array. The method and the apparatus subsamples a plurality (L2) of pixels by: storing L2 analog reset charges output from the L2 pixels into a first set of (N2) storage capacitors, and combining the (L2) reset charges; storing L2 analog image signal charges output from the L2 pixels into a second set of (N2) storage capacitors, and combining the (L2) image charges; and then obtaining a differential voltage (VS-VR) by subtracting (in the analog-domain) the voltage (VR) represented by the combined (L2) reset charges from the voltage (VS) represented by the combined (L2) image signal charges. When L equals one, the circuit performs conventional Correlated Double Sampling CDS upon the one pixel.