Charge-to-Digital Timer Calibration for Low-Noise PLL Phase Quantization
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Solution Overview
Problem
Conventional calibration techniques for Time-to-Digital Converters (TDCs) in Phase-Locked Loops (PLLs) lead to increased power dissipation and clock interference, making it difficult to maintain a constant supply voltage, which affects measurement accuracy and battery life.
Innovation Solution
A calibration method that adjusts the capacitive load and charging current of a Charge-to-Digital Timer based on measured calibration phases, optimizing quantization noise over a large frequency range by using multiple calibration phases with known time differences and corresponding phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay line based phase quantization is used in TDCs for PLLs, then phase measurement capability is achieved, but quantization noise increases with oscillator output frequency
Solution Approach 1:
The patent adjusts the delay line parameters (delay cell values, tap positions) based on the oscillator output frequency to maintain optimal quantization performance across different frequencies. This involves dynamically changing the delay line configuration to compensate for frequency-dependent quantization noise increases.
2Measurement precision
If the delay line is adjusted to maintain quantization performance over frequency, then phase measurement accuracy is maintained, but power dissipation of the PLL increases
Solution Approach 1:
The patent implements dynamic adjustment of the delay line configuration based on the detected oscillator frequency. The system selectively enables or disables specific delay cells and tap positions according to the operating frequency range, optimizing the balance between measurement accuracy and power consumption for each frequency band.
3Measurement precision
If delay line adjustment is implemented to maintain quantization performance, then phase measurement accuracy is maintained, but clock interference increases disturbing PLL operation
Solution Approach 1:
The patent applies different delay line configurations and activation patterns for different frequency ranges. By locally optimizing the delay line usage for specific frequency bands, the system maintains measurement accuracy while minimizing the generation of clock interference that would otherwise disturb PLL operation at higher frequencies.
4Measurement precision
If delay cells in the delay line are used, then phase quantization is achieved, but supply voltage of the TDC cannot be maintained at a constant level
Solution Approach 1:
The patent implements periodic calibration of the delay line using a calibration signal with a known phase relationship to the oscillator output. This periodic calibration allows the system to measure and compensate for supply voltage variations, maintaining accurate phase quantization despite voltage instability caused by the delay cells' high peak current demands.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes quantization noise and improves the accuracy of phase quantization in TDCs, reducing power dissipation and maintaining a stable supply voltage, thereby enhancing the performance of PLLs.
Implementation Method 1
The basic architecture for a conventional CDT comprises a current source, an integrator, and a flash analog-to-digital converter
Data Source
AI summary
A calibration method disclosed herein calibrates at least one of a capacitive load and a charging current controlling a charge-to-digital timer (CDT). In general, the disclosed calibration method measures multiple calibration phases based on start and stop signals separated by a known time difference, and therefore having a known phase, and adjusts at least one of the capacitive load and the charging current of the CDT based on the measured calibration phases. In so doing, the disclosed calibration method reduces power dissipation and peak supply currents over the frequency range of the CDT.