CDTA Buffer Circuit With Source Followers for Wideband ADC Inputs
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Solution Overview
Problem
Modern high-speed Analog-to-Digital Converters (ADCs) face challenges in achieving sub-picosecond timing resolution and high bandwidth due to RF buffer limitations, particularly in time-interleaved ADC architectures, which result in timing-skew and gain performance issues while increasing power consumption.
Innovation Solution
A buffer circuit utilizing a Current Differencing Transconductance Amplifier (CDTA) with wideband source follower circuits and current-feedback architecture, which enhances bandwidth, reduces sensitivity to parasitic capacitances, and provides high reverse isolation, thereby mitigating the limitations of conventional RF buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional RF buffers are used in time-interleaved ADCs, then the ADC architecture can achieve high aggregate throughput, but the RF buffer limitations (bandwidth, slew-rate, common-mode rejection, reverse isolation) degrade the overall system performance and timing resolution
Solution Approach 1:
The patent introduces a specialized buffer circuit as an intermediary component between the RF front-end and the time-interleaved ADC. This buffer circuit acts as a mediator that specifically addresses the bandwidth and timing-skew limitations of conventional RF buffers, enabling the ADC to achieve sub-picosecond timing resolution while maintaining high aggregate throughput.
Solution Approach 2:
The patent applies local quality by providing dedicated buffering circuitry with optimized characteristics (high bandwidth, low timing-skew) specifically at the ADC input stage where it is most needed. Each sub-ADC in the time-interleaved architecture receives signals through individually optimized buffer paths, allowing local performance enhancement without compromising the overall system throughput.
2Reliability
If the bandwidth and slew-rate of RF buffers are increased to meet timing requirements, then sub-picosecond timing resolution can be achieved, but power consumption increases significantly
Solution Approach 1:
The patent employs parameter changes by optimizing the buffer circuit's electrical characteristics (bandwidth, slew-rate, impedance) to achieve the minimum necessary performance for sub-picosecond timing resolution. The buffer is designed with specific gain-bandwidth products and slew-rates that are tailored to the ADC's sampling rate requirements, avoiding excessive power consumption while meeting timing specifications.
3Ease of manufacture
If conventional RF buffers are used, then the system can operate with standard components, but the buffering limitations set a barrier for overall system and RF transceiver performance
Solution Approach 1:
The patent segments the buffering function into a dedicated buffer circuit module that is distinct from both the RF front-end and the ADC. This segmentation allows the buffer to be optimized independently for high-performance applications while using standard, commercially available components. The modular approach enables high system performance without requiring custom or proprietary components throughout the entire system.
Data Source
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AI summary
A buffer circuit is provided. The buffer circuit includes a Current Differencing Transconductance Amplifier (CDTA) comprising a first input node and a second input node each configured to receive a respective one of a first signal and a second signal. The buffer circuit further includes a first source follower circuit coupled to a first output node of the CDTA and configured to generate a first buffer output signal based on a first output signal of the CDTA. Additionally, the buffer circuit includes a second source follower circuit coupled to a second output node of the CDTA and configured to generate a second buffer output signal based on a second output signal of the CDTA. The buffer circuit further includes a first feedback path comprising at least one of a first resistive element and a first capacitive element. The first feedback path couples an output node of the first source follower circuit to the first input node of the CDTA. In addition, the buffer circuit includes a second feedback path comprising at least one of a second resistive element and a second capacitive element. The second feedback path couples an output node of the second source follower circuit to the second input node of the CDTA.