CEEPROM Cell Direct Digital Output Without Sense Amplifiers
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Solution Overview
Problem
Conventional EEPROM devices require high power consumption due to the need for sense amplifiers and current comparators to read digital signals, which increases DC current consumption and complicates the reading process.
Innovation Solution
A Complementary Electrical Erasable Programmable Read Only Memory (CEEPROM) cell is designed with two re-configurable non-volatile elements and one access transistor, allowing direct output of digital signals '1' or '0' without a sense amplifier, reducing power consumption and simplifying the reading process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional EEPROM devices use sense amplifiers and current comparators to read digital signals, then the reading process can be performed, but the power consumption increases and the device complexity increases
Solution Approach 1:
The patent extracts and removes the sense amplifier and current comparator components from the EEPROM device. By eliminating these power-consuming components, the invention achieves direct digital signal output from the memory cell, resolving the contradiction between readable operation and power consumption.
Solution Approach 2:
The memory cell is designed to directly output digital signals without requiring external sense amplification or comparison circuitry. The cell itself performs the function of generating readable digital output, eliminating the need for separate reading components and reducing overall power consumption.
2Ease of operation
If conventional EEPROM devices use sense amplifiers and current comparators, then digital signals can be read, but the device complexity increases
Solution Approach 1:
The patent removes the sense amplifier and current comparator components from the device architecture. This extraction simplifies the overall device structure while maintaining the ability to read digital signals directly from the memory cell, resolving the contradiction between operational capability and device complexity.
3Loss of information
If conventional EEPROM devices use DC currents for reading, then digital information can be output, but the current consumption exceeds 100 μA per cell
Solution Approach 1:
The memory cell directly outputs digital voltage signals without requiring external DC current sources or sense amplifiers. This self-service approach eliminates the need for high current consumption during read operations, resolving the contradiction between information output capability and energy loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
CEEPROM achieves low power consumption and fast-access solutions by eliminating the need for sense amplifiers and current comparators, offering compatibility with digital circuitries and silicon area savings in embedded applications.
Implementation Method 1
The charge storing memory cell 120 is a MOSFET with a layer of charge storage material 122 under the control gate 124 and above the channel surface of a MOSFET. The amounts of charges in the storing layer 122 can affect the threshold voltage applied to the control gate 124
Implementation Method 2
The access transistor 110 is activated to attach to the bitline by applying a voltage bias VG. A current source configured with a constant voltage bias VR to one node of a load device 220 and the other node connected to the bitline passes electrical current ICELL through the access transistor 110
Data Source
AI summary
Complementary Electrical Erasable Programmable Read Only Memory (CEEPROM) is disclosed. CEEPROM cell comprises a pair of non-volatile memory elements and one access transistor. The two elements of the non-volatile memory pair are configured to be one with high electrical conductance and the other with low electrical conductance. The positive voltage VDD for digital value “1” and ground voltage VSS for digital value “0” are connected to the two input nodes of the two non-volatile elements respectively after configuration. The digital signal either VDD or VSS passed through the high conductance non-volatile memory element in the pair is directly accessed by the access transistor without applying a sense amplifier as the conventional EEPROM would require. Without sense amplifiers, the digital data in CEEPROM can be fast accessed. The power consumption and the silicon areas required for sense amplifiers can be saved as well.