Cell Abutment Optimization for Chip Layout Routing
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Solution Overview
Problem
Electronic design automation (EDA) tools face challenges in optimizing cell placements in chip layouts due to increasingly complex design rules and constraints, leading to inefficiencies in layout effort and simulation performance.
Innovation Solution
A computer-implemented method for generating a cell-based chip layout using a cell abutment process, which involves selecting cells from a library, performing place-and-route operations, and rearranging cells to achieve optimal placement and routing, ensuring clean design rule checks and meeting complex design demands through iterative processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional place-and-route operations are used with complex design rules, then design completeness is maintained, but layout effort and time increase significantly
Solution Approach 1:
The patent applies preliminary action by performing cell abutment optimization before the main place-and-route operations. The system identifies and abuts cells that can be placed adjacent to each other based on design rules, creating an optimized initial placement that reduces subsequent routing complexity and improves overall layout efficiency.
Solution Approach 2:
The patent segments the complex placement problem into two phases: first, abutment placement of compatible cells based on design rules, and second, conventional place-and-route operations for remaining cells. This segmentation simplifies the overall problem by handling rule-constrained cells separately, reducing the computational burden on the main routing algorithm.
2Area of stationary object
If cells are placed densely to improve integration, then area utilization increases, but design rule violations increase
Solution Approach 1:
The patent applies local quality by evaluating design rule compliance locally for each cell placement decision. The system checks specific design rules applicable to each cell pair and only abuts cells that satisfy the relevant rules, ensuring local compliance while achieving global area optimization through selective cell abutment.
3Productivity
If iterative rearrangement of cells is performed to optimize placement, then routing efficiency improves, but computational time increases
Solution Approach 1:
The patent performs cell abutment as a preliminary action before main routing operations, establishing an optimized placement configuration upfront. This preliminary optimization reduces the number of iterative rearrangements needed during subsequent routing, thereby improving routing efficiency while minimizing additional computational time.
Data Source
AI summary
The present disclosure is directed to systems and methods for cell placement. In embodiments, the methods include placing a plurality of cells selected from a cell library in a chip design to produce a first cell placement and determining whether the first cell placement satisfies design demands. In further embodiments, the method also includes rearranging a first cell to abut the first cell with a second cell when the first cell placement fails to satisfy design demands. In still further embodiments, the first cell is rearranged until a second cell placement providing a minimum metal route between the first and second cells is determined. In various embodiments, the method further includes generating a design layout based on the second cell placement and outputting the design layout to a machine readable storage medium. The outputted layout is used to manufacture a set of masks used in chip fabrication processes.