Vertical Channel Memory Cell Contacts Without Extra Interconnects
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing integration density, improving operation speed, and enhancing electrical and reliability characteristics due to the need for additional interconnection layers that increase device size and deteriorate performance.
Innovation Solution
The semiconductor device incorporates vertical channel transistors with integrated bit line and word line contacts directly on the cell array region, eliminating the need for additional interconnection layers, thereby reducing device size and improving electrical and reliability characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional interconnection layers are added to connect bit lines and word lines, then electrical connection is achieved, but device size increases and fabrication cost increases
Solution Approach 1:
The patent merges the functions of bit line contacts and word line contacts by forming both contacts through the same contact hole in the insulating layer. This integration eliminates the need for separate interconnection layers, reducing device area while maintaining reliable electrical connections to both bit lines and word lines simultaneously
Solution Approach 2:
The contact structure serves multiple functions: it provides electrical connection to bit lines, electrical connection to word lines, and acts as an interconnection point between them. This multi-functional design eliminates the need for additional dedicated interconnection layers, thereby reducing device size and fabrication complexity
2Reliability
If additional interconnection layers are added to connect bit lines and word lines, then electrical connection is achieved, but fabrication cost increases
Solution Approach 1:
The patent combines the formation of bit line contacts and word line contacts into a single fabrication step through the same contact hole. This merging reduces the number of fabrication layers and steps required, directly lowering manufacturing complexity and cost while ensuring reliable electrical connections
Solution Approach 2:
The patent extracts and eliminates the unnecessary additional interconnection layers from the device structure. By removing these redundant layers while maintaining essential electrical connections through the integrated contact design, fabrication cost is reduced without compromising connection reliability
3Quantity of substance
If vertical channel transistors are used to increase integration density, then transistor density improves, but device complexity increases
Solution Approach 1:
The patent applies merging principles to the contact structure, where bit line contacts and word line contacts are formed together through the same contact hole. This simplifies the overall device structure and reduces fabrication complexity, allowing vertical channel transistors to achieve high integration density without proportionally increasing device complexity
Data Source
AI summary
A semiconductor device may include a substrate including a cell array region, data storage patterns on the cell array region and spaced apart from each other in a first direction and a second direction that are parallel to a top surface of the substrate, word lines on the data storage patterns, extending in the second direction, and spaced apart from each other in the first direction, bit lines on the word lines to cross the word lines, extending in the first direction, and spaced apart from each other in the second direction, an insulating pattern on the bit lines, bit line contacts in the insulating pattern and electrically connected to the bit lines, respectively, and word line contacts in the insulating pattern between the bit lines and electrically connected to the word lines, respectively. The bit line contacts and the word line contacts may be on the cell array region.