Cell-Aware ATPG Using Fault Rules and SDF for Internal Defect Detection
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Solution Overview
Problem
Conventional fault models and test patterns for integrated circuit (IC) chips are inadequate in detecting defects within standard cells, as they primarily focus on faults at cell inputs, outputs, and interconnects, failing to effectively address internal defects such as shorts and opens within cells, which are becoming more critical as IC complexity increases and the demand for zero-defect silicon grows.
Innovation Solution
A system employing timed transition ATPG techniques generates cell-aware test patterns by using fault rules files and delay information from SDF files, along with node slack information, to specifically target defects inside standard cells, enabling more comprehensive defect detection within the IC chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional fault models are used that focus on cell inputs and outputs, then test pattern generation is simpler, but detection of internal cell defects (shorts and opens) is inadequate
Solution Approach 1:
The patent segments the cell testing process into multiple phases: fault activation phase and fault propagation phase. It further divides test patterns into two-cycle test patterns with specific phases (first phase for activation, second phase for propagation). This segmentation allows systematic coverage of internal cell defects while maintaining structured test generation
Solution Approach 2:
The patent performs preliminary actions by pre-calculating and storing fault rules in lookup tables before actual testing. The fault rules engine pre-generates fault rules files containing activation and propagation rules for various defect types (shorts, opens) at different cell locations. This preliminary preparation enables efficient test generation without complex real-time calculations during actual testing
2Reliability
If more comprehensive test patterns are generated to detect internal cell defects, then defect detection effectiveness improves, but test application time increases
Solution Approach 1:
The patent uses copying by creating standardized fault rules that can be replicated across multiple cell instances. The fault rules engine generates template-based fault rules that are copied and applied to different cell types and instances, avoiding redundant analysis for each individual cell while ensuring comprehensive coverage
Solution Approach 2:
The patent performs preliminary action by pre-computing fault rules and storing them in lookup tables. The fault rules files are generated beforehand containing all necessary activation and propagation rules for various defect scenarios. During actual testing, these pre-computed rules are directly applied without recalculation, significantly reducing test application time while maintaining high test quality
3Measurement precision
If cell-aware test patterns are generated using timing information, then detection of delay defects improves, but processing complexity increases
Solution Approach 1:
The patent introduces an intermediary component: the fault rules engine that acts as a mediator between the ATPG system and timing information (SDF files). This engine processes timing data and converts it into standardized fault rules, shielding the rest of the system from direct complexity of timing analysis while enabling precise delay defect detection through the intermediary's processed rules
Data Source
AI summary
A fault rules engine generates a plurality of fault rules files, each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design. Each fault rules file includes data quantifying a nominal delay for a given two-cycle test pattern and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects of a given cell type of the plurality of cell types in the IC design. An IC test engine extracts an input to output propagation delay for each cell instance from a standard delay format (SDF) file for the IC design and generates cell-aware test patterns for each cell instance of each cell type in the IC design based on the plurality of fault rules files and the extracted input to output propagation delays.