Cell-Aware Defect Characterization via Inter-Cell Timing Analysis
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Solution Overview
Problem
Current methods for testing complex integrated circuits face challenges in accurately detecting defects due to the complexity of standard library cells, where simplistic testing methods fail to determine the source of failures and accurately model the behavior under varying RC loading conditions, especially with increasing complexity and low power consumption leading to significant timing variations.
Innovation Solution
A cell-aware defect model is developed that considers different timing effects caused by inter-cell capacitance or load capacitance, using a range of RC values to model fault conditions, allowing for more accurate defect detection by varying load conditions and timing arcs, and documenting detection status in defect detection tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If simplistic testing methods are used, then testing complexity is reduced, but defect detection accuracy deteriorates
Solution Approach 1:
The patent segments the testing process by creating separate defect detection tables for different load conditions (first load condition and second load condition). Each table captures defect behavior under specific timing arcs, allowing complex timing analysis to be broken down into manageable segments that can be independently analyzed and combined.
Solution Approach 2:
The patent performs preliminary action by pre-computing defect detection tables for various load conditions and timing arcs before actual testing. This pre-characterization of defect behavior under different conditions allows the testing system to quickly reference predetermined data rather than performing complex simulations during runtime, reducing testing complexity while maintaining accuracy.
2Measurement precision
If cell-aware defect models with multiple load conditions are used, then defect detection accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent merges the results from multiple defect detection tables (each corresponding to different load conditions) into a comprehensive defect characterization. By combining the data from first load condition tables and second load condition tables, the system achieves accurate defect detection across varying RC loading conditions without having to perform all computations simultaneously, thus managing computational complexity.
Solution Approach 2:
The patent applies preliminary action by pre-computing and storing defect detection tables for various load conditions and timing arcs. This allows the complex computational work to be performed in advance during model creation, rather than during actual defect testing, thereby reducing the computational burden during runtime while maintaining high defect detection accuracy.
3Measurement precision
If timing variations due to low power consumption are considered, then defect characterization accuracy is improved, but analysis complexity increases
Solution Approach 1:
The patent applies parameter changes by systematically varying the load conditions (RC values) and timing arcs as parameters in the defect model. By creating defect detection tables for different combinations of these parameters, the system captures the effect of timing variations due to low power consumption on defect behavior, improving characterization accuracy while managing analysis complexity through structured parameter exploration.
Data Source
AI summary
Disclosed is cell-aware defect characterization by considering inter-cell timing. Also disclosed is a method and apparatus that determines whether a defect can be detected in a standard library cell used to design an integrated circuit. A defect detection table is generated that indicates whether particular defects can be detected with particular combinations of input logic states and under varying load conditions. Results are merged to provide a single metric for each combination of input and output logic states that indicates one of three possible results for each defect: (1) whether the defect can be detected under all load conditions, (2) whether the defect can be detected only under some load conditions; or (3) whether the defect cannot be detected for the particular combination of input logic states regardless of the load conditions.