Cell-Aware SDD ATPG Using Timing Data for IC Defect Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional fault models and test patterns for integrated circuit (IC) chips are inadequate in detecting cell-aware delay defects, particularly small delay defects (SDDs), as they primarily focus on faults at cell inputs and outputs, neglecting internal defects within standard cells, and are less effective with increasing IC complexity and smaller geometries.
Innovation Solution
The development of a system that generates cell-aware test patterns using SDD ATPG techniques, which extract input-to-output propagation delays and node slack information from SDF files and node slack reports to target candidate defects inside standard cells, employing the longest possible path for defect detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional fault models are used that focus on cell inputs and outputs, then test generation is simpler and faster, but detection of cell-aware delay defects (especially SDDs) is inadequate
Solution Approach 1:
The patent segments the test generation process into distinct phases: fault activation and fault propagation. It further segments defects into categories (major defects, small delay defects, intermediate delay defects) and targets them with different test pattern strategies. This segmentation enables precise targeting of SDDs while managing overall test complexity.
Solution Approach 2:
The patent applies local quality by creating cell-specific test patterns that target defects within individual standard cells rather than using uniform netlist-level test patterns. It extracts cell timing information and generates tailored test patterns for each cell type, enabling precise detection of internal cell defects while maintaining efficiency through reuse of cell-level test patterns across multiple cell instances.
2Reliability
If test patterns target internal cell defects, then defect detection quality improves, but test application time increases due to more patterns required
Solution Approach 1:
The patent performs preliminary extraction of cell timing information from SDF files and pre-characterizes cell behavior before generating test patterns. It pre-identifies candidate defects and their expected timing characteristics, allowing test patterns to be generated more efficiently and applied faster during actual testing while maintaining high detection quality.
Solution Approach 2:
The patent applies partial action by focusing test efforts on the most critical defect types (particularly SDDs and intermediate delay defects) rather than attempting to detect all possible defects with equal thoroughness. It uses targeted test patterns that apply sufficient testing depth for critical defects while reducing testing overhead for less critical areas, optimizing the balance between test quality and time.
3Adaptability or versatility
If IC chip geometry is reduced and complexity increased, then device functionality improves, but conventional test patterns become less effective at detecting defects
Solution Approach 1:
The patent changes the parameters used for test pattern generation by incorporating cell timing information (arrival times, required times, slack values) from SDF files. It uses these timing parameters to generate test patterns specifically optimized for detecting small delay defects in modern scaled technologies, rather than relying on conventional netlist-level parameters that are inadequate for detecting SDDs in complex, scaled ICs.
Data Source
AI summary
An integrated circuit (IC) test engine extracts an input to output propagation delay for each cell instance of each of a plurality of cell types in an IC design from an SDF file for the IC design. The IC test engine extracts a node slack of each cell instance of each of the plurality of cell types of the IC design from a node slack report. The IC test engine also generates cell-aware test patterns for each cell instance of each cell type in the IC design to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of a plurality of candidate defects characterized in the plurality of fault rules files. Each cell-aware test pattern is configured to sensitize and propagate a transition along the longest possible path to test small delay defects in cell instances of the fabricated IC chip.