Cell-Aware Test Patterns for Internal IC Defect Detection
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Solution Overview
Problem
Conventional fault models for integrated circuit (IC) chips are inadequate as they only consider defects on cell inputs, outputs, and interconnects, failing to detect internal defects within standard cells, which becomes a challenge as IC complexity increases and the demand for zero-defect silicon grows.
Innovation Solution
A system employing a fault rules engine to generate fault rules files for each cell type in an IC design, including data on nominal and delta delays for two-cycle test patterns, enabling the IC test engine to create cell-aware test patterns that target specific defects inside cells, such as shorts and opens, using untimed ATPG techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fault models are used that only consider defects on cell inputs, outputs, and interconnects, then the testing process is simple and fast, but internal defects within standard cells cannot be detected
Solution Approach 1:
The patent segments the testing approach by introducing cell-aware test patterns that specifically target internal cell defects, separating the detection of interconnect defects (conventional) from internal cell defects (new). This segmentation allows comprehensive defect coverage while managing complexity through structured test pattern generation based on cell layout analysis.
Solution Approach 2:
The patent adds a new dimension to testing by moving from netlist-level abstraction to layout-level analysis. By incorporating physical cell layout information and identifying potential defect locations within cell boundaries, the approach detects defects in a previously untested dimensional space (internal cell structures), thereby improving reliability without proportionally increasing complexity.
2Measurement precision
If cell-aware test patterns are generated to detect internal cell defects, then defect detection accuracy improves, but test application time increases
Solution Approach 1:
The patent applies preliminary action by pre-processing cell layout information to identify potential defect locations and characteristics before test pattern generation. By analyzing cell layouts in advance and pre-characterizing internal cell structures, the system prepares defect detection data that speeds up the actual testing phase, thereby improving detection accuracy while mitigating time loss.
Solution Approach 2:
The patent changes key parameters by introducing layout-based defect characteristics (location, type, severity) as new test parameters. By transforming the testing approach from generic stimulus-response to targeted defect-specific patterns based on layout parameters, the system achieves higher detection precision while optimizing test application time through parameter-driven pattern generation.
Data Source
AI summary
A fault rules engine generates a plurality of fault rules files. Each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design, and each fault rules file of the plurality of fault rules files can include data quantifying a nominal delay for a given two-cycle test pattern of a set of two-cycle test patterns and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects for a given cell type in the IC design. An IC test engine generates cell-aware test patterns based on the plurality of fault rules files to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of the plurality of candidate defects characterized in the plurality of fault rules files.