Memory Cell Block Mapping for Sub-Word Line Driver Faults
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Solution Overview
Problem
As memory device capacities increase, the likelihood of defective memory cells increases, making it difficult to fabricate devices without errors, and existing error correction methods struggle to handle the maximum number of error bits caused by sub-word line driver faults.
Innovation Solution
A memory device and system that adjusts the mapping between data pads and cell blocks sharing sub-word line drivers, controlling the number of bits output to prevent uncorrectable errors within the error correction capability of the memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device capacity is increased, then storage capability is improved, but the likelihood of defective memory cells increases
Solution Approach 1:
The memory device is divided into multiple cell blocks (e.g., first cell block, second cell block, third cell block) that can be independently mapped to different data pads. This segmentation allows selective activation of cell blocks based on defect locations, enabling high-capacity memory operation while isolating defective regions to prevent uncorrectable errors.
2Device complexity
If sub-word line drivers are shared among multiple cell blocks, then device complexity is reduced, but error propagation risk increases
Solution Approach 1:
The mapping between cell blocks and data pads is made dynamic and reconfigurable through a mapping circuit. This allows the system to adaptively change which cell blocks are activated and how they are mapped to data pads, enabling the system to respond to detected defects by rerouting data paths and preventing error propagation while maintaining shared sub-word line driver efficiency.
3Device complexity
If mapping between cell blocks and data pads is fixed, then device complexity is reduced, but adaptability to defects decreases
Solution Approach 1:
The mapping circuit implements dynamic reconfigurable mapping between cell blocks and data pads. When defects are detected in specific cell blocks, the mapping circuit can reconfigure which cell blocks are activated and how they map to data pads, allowing the system to adapt to various defect patterns while maintaining efficient use of shared sub-word line drivers.
Solution Approach 2:
The system changes operational parameters by adjusting which cell blocks are activated and how they are mapped to data pads based on defect detection results. This parameter change approach allows the memory device to maintain high-capacity operation while adapting to different defect scenarios without increasing physical hardware complexity.
Data Source
AI summary
A memory device includes a memory cell array including a plurality of cell blocks, each cell block including a plurality of memory cells and sharing sub-word line drivers with adjacent cell blocks; a data input/output circuit configured to input and output data corresponding to the plurality of cell blocks through a plurality of data pads; and a mapping circuit disposed between the memory cell array and the data input/output circuit, and configured to control a mapping between the plurality of cell blocks and the plurality of data pads, while adjusting, according to an output control signal, a number of bits of data output from cell blocks sharing activated sub-word line drivers.