Cell Boundary Interconnect Layout for Denser Standard Cells
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Solution Overview
Problem
The challenge of increasing integration density in integrated circuit devices while maintaining efficient signal routing and minimizing the effective size of standard cells is hindered by practical limitations in reducing the height of standard cells, which often results in increased width, thereby increasing the overall planar area.
Innovation Solution
The integration of lower interconnect metal layers at cell boundaries for both intra-standard cell interconnections and block routing, allowing for reduced planar areas and enhanced integration density by optimizing the use of metal tracks at these boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of standard cells is reduced to increase integration density, then the planar area increases due to increased width, but the goal is to reduce planar area
Solution Approach 1:
The patent utilizes the vertical dimension by integrating lower interconnect metal layers at cell boundaries, allowing signals to route through multiple metal layers (M1, M2, M3) vertically stacked. This three-dimensional metal interconnect architecture enables compact standard cell designs where horizontal routing is supplemented by vertical connections through via structures, effectively converting a two-dimensional routing problem into a three-dimensional solution that reduces planar footprint while maintaining integration density
Solution Approach 2:
The cell boundary metal patterns serve multiple functions simultaneously: they provide intra-standard cell interconnections for signals remaining within the same cell, and they enable block routing for signals transitioning between adjacent cells. This multi-functional use of the same metal infrastructure eliminates the need for separate dedicated routing resources, thereby reducing overall planar area while achieving high integration density
2Productivity
If metal tracks are optimized at cell boundaries for intra-standard cell interconnections, then routing efficiency improves, but device complexity increases
Solution Approach 1:
The patent merges intra-standard cell interconnection paths with block routing paths by allowing the same cell boundary metal patterns to serve both purposes. Instead of creating separate dedicated metal tracks for local and global routing, the design combines these functions into a unified metal infrastructure that operates at the cell boundary level, improving routing efficiency while managing complexity through consolidation rather than proliferation of separate structures
Data Source
AI summary
Integrated circuit devices are provided. An integrated circuit device includes a substrate and a cell that has a plurality of transistors. The transistors include an upper transistor having an upper channel region. Moreover, the transistors include a lower transistor between the substrate and the upper transistor. The lower transistor includes a lower channel region. The integrated circuit device includes a power line extending longitudinally in a first horizontal direction below the substrate and defining a cell boundary of the cell that extends longitudinally in the first horizontal direction. The integrated circuit device includes a cell boundary signal metal pattern on the cell and extending longitudinally in the first horizontal direction over the cell boundary and connected to at least two transistors of the plurality of transistors. Related methods of forming integrated circuit devices are also provided.