Semiconductor Cell Boundary Isolation With Nonconductive Trenches
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Solution Overview
Problem
Due to the reduction in semiconductor device size, adjacent cells face a short-circuit issue due to insufficient space for metal routing, leading to potential contact between metal strips across cell boundaries.
Innovation Solution
A method is employed to form a separating wall using a non-conductive material on the boundary between cells, preventing metal strips from crossing and short-circuiting by forming trenches and filling them with non-conductive material to create a barrier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the semiconductor device size is reduced to advance manufacturing, then device miniaturization is achieved, but adjacent cells encounter short-circuit issues due to insufficient space for metal routing
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor device into isolated cell units separated by non-conductive walls. These walls segment the metal routing paths, preventing electrical contact between adjacent cells while maintaining miniaturization. The segmentation creates independent routing channels within each cell, solving the short-circuit problem without requiring larger device dimensions.
Solution Approach 2:
The patent introduces non-conductive walls as intermediary structures between adjacent metal strips and cells. These intermediary walls act as barriers that prevent direct electrical contact between metal routing in neighboring cells, thereby eliminating short-circuit risks while allowing the device to maintain its reduced size.
2Productivity
If cell height is reduced for miniaturization, then device density increases, but metal strips from adjacent cells may contact and cause short-circuits
Solution Approach 1:
The patent resolves the isolation problem by transitioning from two-dimensional planar separation to three-dimensional vertical separation. Non-conductive walls extend vertically through the metal routing layers, creating isolation in the vertical dimension rather than relying solely on horizontal spacing. This allows high device density to be achieved while maintaining reliable metal strip isolation.
Solution Approach 2:
The patent applies local quality by providing non-conductive walls specifically at critical boundaries between adjacent cells where short-circuit risks exist, rather than uniformly throughout the entire device. This targeted approach maintains device density while ensuring metal strip isolation only where necessary for preventing short-circuits.
Data Source
AI summary
A method of manufacturing a semiconductor device, including: providing a substrate including a first cell and a second cell; forming a plurality of first metal strips on a first plane; forming a first trench over a boundary between the first cell and the second cell, wherein a bottom surface of the first trench is located on a second plane over the first plane; filling the first trench with a non-conductive material, resulting in a separating wall; and forming a plurality of second metal strips on a third plane over the second plane, wherein the plurality of second metal strips comprise a first second metal strip and a second second metal strip separated from each other by the separating wall.