Cell Boundary Metal Interconnect Layout for Denser Standard Cells
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Solution Overview
Problem
As demands for high performance and high speed in integrated circuit devices increase, there is a need to enhance integration density while managing the practical limitations of reducing standard cell size.
Innovation Solution
The integration of standard cells with metal tracks at cell boundaries that can be used for both lower interconnections and block routing, allowing for reduced planar areas and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If standard cell size is reduced to increase integration density, then integration density is improved, but manufacturing complexity and routing difficulty increase
Solution Approach 1:
The metal track at the cell boundary is designed to serve dual purposes: it functions as a lower interconnection for transistors within the same cell and as a block routing interconnection for adjacent cells. This multi-functionality allows the cell boundary structure to contribute to both intra-cell and inter-cell connectivity, reducing the need for separate dedicated routing structures and thereby managing complexity while maintaining high integration density.
Solution Approach 2:
The patent utilizes the vertical dimension by extending the metal track through multiple layers (from the first metal layer through the second metal layer) at the cell boundary. This three-dimensional approach to interconnection allows signals to pass between cells vertically, reducing the burden on planar routing and enabling more compact cell layouts without proportionally increasing routing complexity.
2Quantity of substance
If standard cell size is reduced to increase integration density, then integration density is improved, but routing efficiency deteriorates
Solution Approach 1:
The cell boundary metal track is designed to simultaneously serve as a lower interconnection for local transistor access and as a block routing path for long-distance signals between cells. This dual functionality ensures that routing efficiency is maintained because signals can utilize the same physical structure for both local and global connectivity, eliminating the need for additional dedicated routing resources that would be required in smaller cells.
Solution Approach 2:
The interconnection structure is segmented into different functional zones: the metal track within the cell serves local interconnection needs, while the extended metal track at the cell boundary serves block routing needs. This segmentation allows each portion of the interconnection structure to be optimized for its specific function, maintaining routing efficiency despite reduced cell size.
3Quantity of substance
If metal tracks at cell boundaries are used for both lower interconnections and block routing, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes the vertical dimension to resolve manufacturing alignment challenges. By extending the metal track through multiple layers (first metal layer, second metal layer) at the cell boundary, the design creates a three-dimensional interconnection structure. This vertical stacking approach reduces the sensitivity to lateral alignment errors between cells, as the vertical connections provide robust pathways that are less affected by planar misalignment, thereby reducing manufacturing precision requirements while maintaining high integration density.
Data Source
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AI summary
Integrated circuit devices are provided. An integrated circuit device includes a substrate (828) and a cell (800) that has a plurality of transistors. The transistors include an upper transistor having an upper channel region (834). Moreover, the transistors include a lower transistor between the substrate (828) and the upper transistor. The lower transistor includes a lower channel region (832). The integrated circuit device includes a power line (822a, 822b) extending longitudinally in a first horizontal direction (X) below the substrate (828) and defining a cell boundary (CB) of the cell (800) that extends longitudinally in the first horizontal direction (X). The integrated circuit device includes a cell boundary signal metal pattern (852) on the cell (800) and extending longitudinally in the first horizontal direction (X) over the cell boundary (CB) and connected to at least two transistors of the plurality of transistors. Related methods of forming integrated circuit devices are also provided.