Semiconductor Memory Cell-Buffer Layers for Buried-Contact Precision
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Solution Overview
Problem
The increasing complexity and difficulty in forming wiring lines and buried contacts in highly integrated semiconductor devices affect the reliability and performance of semiconductor memory devices.
Innovation Solution
The semiconductor memory device incorporates a specific structure with a substrate, element isolation layer, bit lines, cell buffer insulating layers, storage contacts, and information storage units, where the heights and surfaces of various components are configured to optimize contact areas and reduce resistance, including the use of semiconductor epitaxial patterns and conductive layers to enhance connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration of semiconductor devices is increased to reduce size, then more devices can be implemented in the same area, but the process of forming wiring lines and buried contacts becomes increasingly complicated and difficult
Solution Approach 1:
The cell buffer insulating layer is divided into two separate layers: a lower cell buffer insulating layer and an upper cell buffer insulating layer. This segmentation allows for independent formation and optimization of each layer, simplifying the overall manufacturing process while enabling higher device integration density.
Solution Approach 2:
The patent introduces a vertical dimension to the buffer insulating structure by stacking multiple insulating layers at different heights. The lower cell buffer insulating layer is positioned beneath the bit line, while the upper cell buffer insulating layer is positioned above the bit line, creating a three-dimensional insulating architecture that simplifies contact formation.
2Productivity
If the degree of integration is increased, then more semiconductor devices fit in the same area, but manufacturing precision becomes more difficult to achieve
Solution Approach 1:
Dividing the cell buffer insulating layer into lower and upper layers creates distinct manufacturing zones, allowing buried contacts to be formed with greater precision in the lower layer while the upper layer provides additional insulation and structural support.
Solution Approach 2:
The lower cell buffer insulating layer is formed first, establishing a precise reference plane for subsequent buried contact formation. This preliminary action ensures that contacts are formed at the correct depth and position before the upper insulating layer is added.
3Reliability
If contact areas are increased to reduce resistance, then connectivity improves, but device area increases
Solution Approach 1:
The patent extends the contact structure vertically by forming the lower storage contact to extend through the lower cell buffer insulating layer and make contact with the active region at a depth that increases the contact area without increasing the lateral footprint of the device.
Solution Approach 2:
The lower storage contact is nested within the lower cell buffer insulating layer, allowing the contact to extend vertically through the insulating layer to reach the active region. This nested configuration increases the effective contact area while maintaining a compact device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the reliability and performance of semiconductor memory devices by increasing contact areas and reducing resistance, thereby enhancing the overall functionality and efficiency of the device.
Implementation Method 1
a lower storage contact on a plurality of sides of the bit line and comprising a semiconductor epitaxial pattern
Data Source
AI summary
A semiconductor memory device includes a substrate comprising an element isolation layer, a bit line that extends on the substrate in a first direction, a cell buffer insulating layer between the bit line and the substrate and comprising an upper cell buffer insulating layer and a lower cell buffer insulating layer, a lower storage contact disposed on a plurality of sides of the bit line and comprising a semiconductor epitaxial pattern, a storage pad on the lower storage contact and connected to the lower storage contact and an information storage unit on the storage pad and connected to the storage pad, wherein the upper cell buffer insulating layer is between the lower cell buffer insulating layer and the bit line, and each of the lower cell buffer insulating layer and the upper cell buffer insulating layer comprises an upper surface and a lower surface that are opposite to each other.