Cell Delay Change Modeling for IC Design Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing design automation tools are ineffective in capturing delay changes due to modifications in integrated circuit cell parameters, such as gate length, which hinders efficient optimization and requires costly characterization of numerous cell variants.
Innovation Solution
A computer-implemented modeling methodology that estimates delay changes by modifying cell characteristics like gate length, using a phenomenological model based on device equations with empirical fitting parameters, and introduces the concept of output short-circuit voltage (VSC) to correlate with delay changes, enabling more accurate delay modeling and optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If cell parameters are modified to optimize performance, then leakage power is reduced, but delay changes cannot be accurately captured
Solution Approach 1:
The patent changes the parameter being measured from raw delay values to delay changes relative to a reference cell. By modeling ΔD as a function of modified cell parameters (gate length, width, etc.), the system can accurately capture delay variations while enabling performance optimization through parameter modification.
Solution Approach 2:
The patent replaces extensive physical characterization of numerous cell variants with a phenomenological mathematical model. Instead of measuring and storing delay data for each possible cell configuration, the system uses a compact model with fitting parameters that can predict delay changes for any cell parameter modification.
2Measurement precision
If numerous cell variants are characterized to capture delay changes, then measurement precision improves, but device complexity and characterization cost increase
Solution Approach 1:
The patent extracts the essential characteristics of cell delay behavior into a simplified phenomenological model. By identifying and modeling only the key parameters (gate length, width, and their interaction terms) that influence delay changes, the system captures accurate delay information without requiring complete characterization of all cell variant details.
Solution Approach 2:
The patent transforms the cell library from containing discrete characterized variants to containing a continuous model that can generate delay predictions for any parameter values. This parameter-based approach replaces the need for extensive discrete cell variant characterization with a compact mathematical representation.
3Device complexity
If existing delay models are used, then device complexity is minimized, but measurement precision of delay changes deteriorates
Solution Approach 1:
The patent includes higher-order interaction terms (e.g., ΔL·ΔW) in the delay change model beyond what simpler models provide. These additional terms capture non-linear effects and parameter interactions that improve accuracy without substantially increasing model complexity, representing a balanced approach between model simplicity and precision.
Data Source
AI summary
An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.