Cell String Group Erase Verify for Uniform NAND Memory Timing

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Solution Overview

Problem

There is a time difference in erase verify operations between the first and last cell strings when performed on a cell string basis, leading to inefficiencies in nonvolatile memory devices.

Innovation Solution

A memory device that performs erase verify operations on a cell string group basis, applying different erase verify voltages to each group and using a controller to suspend and resume erase operations based on command counts, ensuring consistent verification across all cell strings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If erase verify operation is performed on a cell string basis, then verification can be conducted on individual cell strings, but a time difference occurs between the first and last cell strings processed

Engineering Contradiction:
Improveverification accuracyVSAvoidtime difference
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent merges multiple cell strings into a cell string group and performs erase verify operations on the group simultaneously rather than individually. This combines the verification process for multiple cell strings into a single operation, eliminating the time differences that would occur when processing cell strings sequentially one by one.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent segments the memory structure into cell string groups where multiple cell strings are grouped together and processed as a unit. This segmentation allows the erase verify operation to be applied to multiple cell strings simultaneously through the group structure, reducing the total time required compared to individual cell string processing.

Inventive Principle:
Principle #1Segmentation

2Reliability

If different erase verify voltages are applied to cell string groups, then verification consistency is improved, but device complexity increases

Engineering Contradiction:
Improveverification consistencyVSAvoidcontrol complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different erase verify voltages to different cell string groups based on their specific characteristics or positions. Each cell string group receives a customized verify voltage tailored to its requirements, which improves verification consistency and reliability while the controlled differentiation manages complexity through localized adaptation rather than uniform treatment.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20260038611A1Memory device for performing erase verify operation on cell string group basis and method of operating the same
Publication Date: 2026.02.05 SK HYNIX INC
  • US20260038611A1 patent drawing
  • US20260038611A1 patent drawing
  • US20260038611A1 patent drawing

AI summary

Provided herein may be a memory device for performing an erase verify operation on a cell string group basis, and method of operating the same. The memory device may include a plurality of memory blocks, each including a plurality of cell string groups, a peripheral circuit configured to perform an erase verify operation on a memory block selected from among the plurality of memory blocks, and an erase operation controller configured to control the peripheral circuit to perform the erase verify operation in units of cell string groups within the selected memory block. The erase operation controller controls the peripheral circuit to apply, during the erase verify operation, different erase verify voltages to the selected memory block whenever the erase verify operation is performed on each of the cell string groups.