Cell Inferiority Test Circuit Timing Margin Adjustment
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Solution Overview
Problem
Conventional cell inferiority test circuits face performance issues due to insufficient timing margins between the strobe signal and compression data on global input/output lines, particularly exacerbated by PVT variations in high-density semiconductor memory chips.
Innovation Solution
The proposed cell inferiority test circuit incorporates a compression data generator, a strobe signal delayer, and an input/output line driver, where the strobe signal is delayed by adjustable periods set by test signals to synchronize with compression data, ensuring a sufficient timing margin for effective data transfer on global input/output lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data compression test mode is employed to shorten testing time, then productivity is improved, but timing margin becomes insufficient leading to reliability degradation
Solution Approach 1:
The strobe signal delay amount is made dynamically adjustable through test control signals, allowing the timing margin to be optimized for different testing conditions. The delay circuit enables the strobe signal timing to be flexibly adjusted to ensure sufficient setup and hold times for reliable data latching while maintaining high-speed compression testing.
Solution Approach 2:
The timing parameter of the strobe signal is changed by introducing a variable delay mechanism. The delay amount can be adjusted based on PVT variations and testing requirements, transforming the fixed timing relationship into a可调 parameter that ensures reliable operation across different conditions while maintaining high testing speed.
2Quantity of substance
If integration density is increased to improve productivity, then more cells are tested per chip, but testing time extends reducing productivity
Solution Approach 1:
Multiple cell test results are merged into compressed data that is transmitted through shared global input/output lines. By combining test results from multiple cells accessed by the same address into a single data stream, the circuit achieves efficient parallel testing of large numbers of cells without proportionally increasing testing time.
Solution Approach 2:
The global input/output lines serve multiple functions: they are used for both normal data input/output operations and for transmitting compressed test results from multiple cells. This multi-functionality allows the same physical infrastructure to support both high-density cell integration and efficient testing without requiring additional dedicated test lines.
3Speed
If strobe signal timing is advanced to improve productivity, then data transfer speed increases, but timing margin becomes negative causing setup/hold time violations
Solution Approach 1:
A delay circuit is introduced as an intermediary between the strobe signal generation and the global input/output lines. This intermediary component provides precise timing control, allowing the strobe signal to be delayed by an optimized amount that ensures sufficient setup and hold times while maintaining the highest possible data transfer speed.
Solution Approach 2:
The delay amount is predetermined and optimized based on PVT variations and circuit characteristics. By pre-calculating and setting the appropriate delay value before testing, the circuit ensures that timing margins are sufficient for reliable operation while maximizing data transfer speed, avoiding the need for real-time timing adjustments during testing.
Data Source
AI summary
A cell inferiority test circuit includes a compression data generator configured to compress selected data in response to selection signals and to generate compression data including information about cell inferiority, a strobe signal delayer configured to delay a strobe signal by an amount of time set by a test signal and to generate a delayed strobe signal, and an input/output line driver configured to receive the compression data in sync with the delayed strobe signal and to drive a global input/output line.