Standard Cell Layout Generation Using Archetype Templates
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Solution Overview
Problem
As process technologies shrink below 20 nm, the complexity of design rules for integrated circuits increases, making it difficult to automate the generation of standard cells that conform to these rules, as simple modifications to existing cells are no longer sufficient for producing variants with different drive strengths or forms.
Innovation Solution
A computer-implemented method and system for generating a layout of a cell that involves obtaining an archetype layout conforming to the target process technology's design rules, performing schematic sizing operations on a process technology-independent schematic, and using the archetype layout to generate a process technology-dependent layout, enabling the creation of cells that adhere to complex design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If process technology shrinks below 20 nm to achieve higher integration density, then manufacturing precision and device performance improve, but design rule complexity increases making automation difficult
Solution Approach 1:
The patent segments the cell generation process into distinct phases: obtaining archetype layout, performing schematic sizing operations, and generating the final process technology-dependent layout. This segmentation allows each phase to be handled with appropriate complexity levels, making automation feasible despite overall system complexity
Solution Approach 2:
The patent introduces an archetype layout as an intermediary representation that captures the essential layout structure in a process technology-independent manner. This intermediary serves as a bridge between the schematic design and the final technology-specific layout, simplifying the automation process by decoupling design logic from manufacturing constraints
2Productivity
If automated tools are used to generate cell layouts, then productivity improves, but the ability to handle complex design rules below 20 nm deteriorates
Solution Approach 1:
The patent performs preliminary actions by obtaining an archetype layout that pre-encodes compliance with complex design rules. This archetype serves as a validated template that automatically ensures design rule conformity when reused, eliminating the need for complex real-time checking during automated generation while maintaining high productivity
Solution Approach 2:
The patent changes parameters by transitioning from process technology-independent schematic representations to process technology-dependent layouts. This parameter transformation allows the same archetype to be adapted to different process nodes (e.g., 14 nm, 10 nm) by adjusting specific layout parameters while maintaining structural compliance with respective design rules
3Adaptability or versatility
If multiple variants of standard cells are produced to cover different drive strengths and forms, then adaptability improves, but device complexity and manual design effort increase
Solution Approach 1:
The patent applies universality by creating a single archetype layout that can serve multiple functions across different process technologies and cell variants. Instead of maintaining separate designs for each variant, the universal archetype can be adapted through parameter changes to generate diverse cell types (different drive strengths, forms, etc.), significantly reducing the total number of designs needed while maintaining full adaptability
Data Source
AI summary
A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.