Semiconductor Cell Layout Using Backside Signal Tracks to Cut Height
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Solution Overview
Problem
The requirement of at least four frontside signal tracks for signal routing in complex semiconductor cells impedes the reduction of cell height and device size, especially in 3D-stacked semiconductor devices with backside power delivery networks.
Innovation Solution
A cell architecture is proposed with at most three frontside signal tracks on the same level and one backside signal track, connected to FEOL or MOL structures, optimizing signal routing without additional upper-level metal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If at least four frontside signal tracks are used for signal routing in complex semiconductor cells, then signal routing capability is improved, but cell height increases
Solution Approach 1:
The patent introduces backside signal tracks as a new dimension for signal routing. Instead of increasing the number of frontside signal tracks horizontally, the invention utilizes the vertical dimension by routing signals through the backside of the semiconductor cell. This allows signal routing capability to be improved without increasing cell height, as signals can now traverse through multiple layers (frontside and backside) rather than requiring more parallel tracks at the same level.
2Length of stationary object
If the number of metal line tracks is reduced to scale down cell height, then cell height is reduced, but signal routing capability deteriorates
Solution Approach 1:
The patent segments the signal routing function into multiple independent paths: frontside signal tracks for certain signals and backside signal tracks for other signals. This segmentation allows the total number of metal line tracks to be reduced while maintaining signal routing capability, as the routing function is distributed across different spatial locations (frontside and backside) rather than requiring all signals to traverse through a large number of parallel tracks at a single level.
3Adaptability or versatility
If frontside signal tracks are increased for complex signal routing, then signal routing flexibility is improved, but device area increases
Solution Approach 1:
The patent utilizes the backside dimension to provide additional signal routing paths without increasing the planar footprint of the device. By routing signals through the backside, the invention effectively adds routing flexibility in the vertical dimension rather than requiring more horizontal space, thus improving signal routing flexibility while maintaining compact device area.
Data Source
AI summary
Provided is a cell architecture for a semiconductor device, which includes: at most thee frontside signal tracks provided at a same level on a front side of a semiconductor cell and extended in a 1st direction in parallel with a 1st boundary or a 2nd boundary of the semiconductor cell, the 1st boundary facing the 2nd boundary in a 2nd direction intersecting the 1st direction; at least one backside signal track provided on a back side of the semiconductor cell and extended in the 1st direction; and at least one signal line provided in at least one of the at most three frontside signal tracks and the at least one backside signal track and connected to at least one front-end-of-line (FEOL) structure or at least one middle-of-line (MOL) structure in the semiconductor cell, wherein the at most three frontside signal tracks are arranged in the 2nd direction with a predetermined pitch, and wherein a sum number of the at most three frontside signal tracks and the at least one backside signal track is four.