Cell Layout Architecture for Power Rail Routing Without Jogs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing power routing schemes in integrated circuits require significant routing resources due to the need for numerous jogs connecting power rails to transistors, which can lead to inefficient use of chip area and potential abutment issues between cells.
Innovation Solution
A layout architecture that allows for power rails to be connected through metal layers with optimized placement of second metal layer strips, extending beyond cell boundaries while maintaining efficient routing and reducing the need for additional metal features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional power routing schemes with numerous jogs are used, then power delivery to transistors is achieved, but routing resources and chip area are significantly consumed
Solution Approach 1:
The patent transitions from planar 2D power routing to 3D vertical routing by utilizing multiple metal layers. Power rails extend vertically through the substrate with contacts connecting to transistors at different depths, eliminating the need for horizontal jogs and reducing chip area consumption while maintaining reliable power delivery.
Solution Approach 2:
The patent merges power delivery functions across multiple metal layers into a unified 3D power network. By combining vertical power rails with horizontal interconnects in a layered architecture, the design achieves efficient power distribution without requiring separate jog features for each transistor connection.
2Reliability
If numerous jogs are formed to connect power rails to transistors, then power routing is achieved, but device complexity increases
Solution Approach 1:
The invention simplifies the routing structure by moving from complex 2D jog-based connections to straightforward 3D vertical rails. Power is delivered through vertical extensions in the metal layers, eliminating the need for multiple jog features and reducing overall routing complexity while maintaining reliable power delivery to all transistors.
Solution Approach 2:
The vertical power rails serve multiple transistors simultaneously by extending through the substrate and providing power to various locations. This multi-functional approach replaces the need for individual jog connections for each transistor, reducing device complexity while ensuring reliable power routing.
Data Source
AI summary
A circuit includes a first metal layer having a first first metal layer strip adjacent to a first boundary and a second first metal layer strip adjacent to a second boundary opposite to the first boundary. The first and second first metal layer strips, the first boundary, and the second boundary are parallel to each other. The circuit further includes a second metal layer having a first second metal layer strip and a second second metal layer strip adjacent to the first second metal layer strip. The first second metal layer strip is connected to the first metal layer strip at the first first metal layer strip and the second second metal layer strip is connected to the first metal layer strip at the second first metal layer strip. Each of the first and the second second metal layer strips are parallel to each other.