Cell-Level Signal Electromigration Analysis
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Solution Overview
Problem
Electromigration in integrated circuits, particularly in signal wires with bidirectional current flow and lower metal layers, poses challenges due to increased current densities and Joule heating, leading to potential open-circuit failures, which traditional analysis methods fail to adequately address.
Innovation Solution
A circuit design system that simulates average charging currents and determines time-to-failure for pin placements within cells, invalidating candidate placements that result in shorter lifespans due to electromigration, and optimizes pin positions to maximize the circuit's lifespan by selecting placements with the longest time-to-failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional EM analysis methods are used focusing on higher metal layers, then analysis complexity is reduced, but EM effects in lower metal layers and signal wires are not adequately addressed
Solution Approach 1:
The patent segments the EM analysis into two distinct parts: (1) traditional EM analysis for higher metal layers connecting cells, and (2) new EM analysis for lower metal layers within cells and signal wires. This segmentation allows each part to be analyzed with appropriate methods, improving overall EM effect coverage without overwhelming complexity
Solution Approach 2:
The patent extends EM analysis from the traditional single dimension of higher metal layers to multiple dimensions by incorporating lower metal layers within cells and signal wires into the analysis scope. This dimensional expansion ensures comprehensive EM effect coverage across all circuit levels
2Ease of operation
If pin placements are selected without EM consideration, then routing simplicity is maintained, but circuit lifespan is reduced due to electromigration
Solution Approach 1:
The patent performs preliminary EM analysis and time-to-failure calculations for all candidate pin placements before final routing decisions. This advance evaluation identifies and eliminates problematic pin placements, ensuring that selected placements optimize circuit lifespan without compromising routing simplicity
Solution Approach 2:
The patent converts the potentially harmful effect of electromigration into a beneficial design constraint by using time-to-failure calculations to guide pin placement selections. This approach transforms EM from a failure mechanism into a optimization criterion that extends circuit lifespan
3Power
If current density increases in signal wires, then signal transmission capability is improved, but Joule heating accelerates EM effects
Solution Approach 1:
The patent implements a feedback mechanism by calculating time-to-failure based on actual current densities in signal wires and using this information to adjust pin placement selections. This feedback loop ensures that high current density configurations that would accelerate EM through Joule heating are identified and avoided
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the circuit's lifespan by identifying and excluding pin locations that would shorten its lifespan due to electromigration, thereby enhancing reliability and durability.
Implementation Method 1
Electromigration (EM) is the transport of metal atoms when an electric current flows through a metallic structure in an integrated circuit (IC)
Implementation Method 2
increased current densities and Joule heating effects that accelerate EM
Data Source
AI summary
A circuit design system includes a simulator that determines an average charging current provided by each current insertion point in a cell and an average charging current along a path in the cell between a reference pin position and a candidate pin position. A candidate pin placement tester updates the average charging current along the path by adding the average charging current of each insertion point to the average charging current along the path to produce an updated average charging current along the path and uses the updated average charging current along the path to determine a time to failure for the cell.


