Co-optimizing Cell Libraries for Digital Circuit Design
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Solution Overview
Problem
Current electronic design automation tools face challenges in optimizing digital circuits with complex integrated circuits, as they struggle to minimize design costs while respecting design constraints and incorporating new cells with different transistor topologies and functionalities.
Innovation Solution
A method for simultaneous optimization of digital circuit design and cell library, which involves mapping an initial design to a set of cells, including virtual cells, to determine a minimum nearly optimum set of cells, while reducing implementation costs and adhering to design constraints, and iteratively refining the cell selection to achieve timing closure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of cells in the library is increased to provide more functionality and transistor topologies, then the design flexibility and performance optimization improve, but the design complexity and implementation costs increase
Solution Approach 1:
The cell library is segmented into multiple categories including virtual cells, real cells, and standardized cells. Each segment serves a specific purpose: virtual cells represent ideal functionalities for exploration, real cells provide practical implementations, and standardized cells ensure compatibility. This segmentation allows designers to navigate through different levels of abstraction and select appropriate cells without being overwhelmed by the entire library at once.
Solution Approach 2:
Virtual cells act as intermediaries between the design requirements and the actual physical cell library. They provide an idealized representation of cell functionalities that can be used during design exploration and optimization, then mapped to real cells in subsequent steps. This intermediary layer decouples the design process from the constraints of the physical library, enabling greater flexibility.
2Reliability
If more new cells with different transistor topologies are incorporated, then the performance and functionality of the design improve, but the implementation costs and design constraints become more difficult to manage
Solution Approach 1:
The methodology performs preliminary mapping using virtual cells before finalizing the design with real cells. This preliminary action allows the design to be optimized for performance using idealized cell models without committing to specific physical implementations. Once the design is optimized, the virtual cells are mapped to real cells, and the library is updated accordingly, ensuring that performance requirements are met while controlling implementation costs.
Solution Approach 2:
The system dynamically changes parameters such as cell dimensions, transistor topologies, and technology node based on design requirements and constraints. By allowing parameter variations within the virtual cell models, the design can explore different performance scenarios and select the optimal configuration before finalizing the implementation, thus balancing performance with manufacturing costs.
3Productivity
If the design is optimized to use fewer cells, then the implementation costs are reduced, but the ability to meet timing closure and performance requirements may be compromised
Solution Approach 1:
The methodology incorporates iterative feedback loops where the design is mapped to cells, evaluated for timing and performance, and then remapped if necessary. The library is updated based on the mapping results, and the process is repeated until timing closure is achieved. This feedback mechanism ensures that the design meets performance requirements while minimizing the number of cells used, as each iteration refines the cell selection based on actual timing data.
Solution Approach 2:
The cell library is treated as a dynamic entity that evolves throughout the design process. Initially, a larger set of virtual cells is available for exploration. As the design progresses and timing constraints are identified, the library is updated to include only the necessary real cells that meet the timing requirements. This dynamic adaptation allows the design to start with maximum flexibility and converge to an optimized solution with fewer cells.
Data Source
AI summary
A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library.