Cell-like Floating Gate Test Structure Height Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing method for manufacturing integrated circuits (ICs) with embedded memory technology faces challenges due to the height disparity between the floating gate test device and memory cell structures, which leads to potential damage and electrical shorting during the formation of logic device structures, especially in future process nodes.
Innovation Solution
A method is introduced to form a floating gate test device with a cell-like top layout, comprising islands and bridges, to reduce the height of the floating gate test device structure, ensuring it is compatible with future process nodes and preventing damage or electrical shorting by evenly depositing an etch-back layer, which reduces the height of both the floating gate test device and memory cell structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the floating gate test device structure is formed with conventional layout, then the test device can be manufactured, but the height disparity between the floating gate test device and memory cell structures causes potential damage and electrical shorting during logic device structure formation
Solution Approach 1:
The floating gate test device structure is segmented into multiple regions including a first region with the floating gate electrode, a second region with the control gate electrode, and a third region that is etched away. This segmentation allows different portions of the structure to have different heights, eliminating the height disparity problem while maintaining test functionality
Solution Approach 2:
The patent introduces a new spatial dimension by creating a three-region layout where the floating gate, control gate, and etched region are arranged in specific spatial relationships. This dimensional reorganization allows the structure to accommodate height variations without causing electrical shorting or damage during subsequent processing
2Adaptability or versatility
If the floating gate test device structure height is reduced to match memory cell structures, then compatibility with future process nodes is achieved, but additional manufacturing steps or complexity may be required
Solution Approach 1:
The patent merges the floating gate test device structure formation with the existing memory cell structure formation process. By using the same etch-back layer and processing steps for both structures, the patent achieves height compatibility without requiring additional manufacturing steps, thus maintaining process simplicity while ensuring future node compatibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the height of both structures, preventing damage and electrical shorting, while maintaining compatibility with future process nodes and ensuring reliable IC manufacturing without additional costs or complexity.
Implementation Method 1
evenly depositing an etch-back layer, which reduces the height of both the floating gate test device and memory cell structures
Data Source
AI summary
Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.