Cell Placement Using Layout-Dependent Stress Effects
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Solution Overview
Problem
Current integrated circuit design methodologies fail to accurately account for layout-dependent stress variations, leading to performance issues due to unintentional and intentional stress generation mechanisms, which complicates the selection and placement of cells in IC designs, and requires extensive physical testing and costly wafer fabrication.
Innovation Solution
A system and method that selects target cells for placement in IC designs by considering hypothetical boundary conditions imposed by neighboring cells, using a cell library with pre-annotated performance information and simulation tools to evaluate cell performance under various stress conditions, reducing the need for physical test fabrications and enabling early adoption of new fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional placement and routing methods are used without considering layout-dependent stress effects, then the design process is simpler and faster, but the electrical performance accuracy of transistors deteriorates significantly (40-50% more dependent on location)
Solution Approach 1:
The patent pre-calculates and stores stress effect parameters for different layout configurations before the actual placement process. By performing stress analysis in advance and creating lookup tables of stress effects for various neighboring cell combinations, the system eliminates the need for complex real-time stress calculations during placement, thereby maintaining high electrical performance accuracy while reducing placement complexity.
Solution Approach 2:
The patent introduces stress effect parameters as an intermediary between the physical layout and electrical performance. These parameters act as a bridge that quantifies the impact of neighboring cells on transistor behavior, allowing the placement tool to account for stress effects without directly simulating complex physical interactions during the placement process.
2Measurement precision
If extensive physical testing and wafer fabrication are conducted to account for stress variations, then the performance evaluation accuracy improves, but the cost and time to market increase significantly
Solution Approach 1:
The patent creates virtual models that copy and simulate the stress effects of physical layouts without requiring actual wafer fabrication. By using computational models to replicate the behavior of transistors under different stress conditions, the system achieves accurate performance evaluation while eliminating the time-consuming and expensive iterative physical testing process.
Solution Approach 2:
The patent performs performance evaluation and stress analysis during the design stage before any physical fabrication occurs. By predicting stress effects and evaluating performance in silico using pre-calculated stress parameters, the system identifies optimal designs early in the development cycle, avoiding costly and time-consuming physical test iterations.
3Reliability
If layout-dependent stress effects are considered in cell selection, then the electrical performance and reliability improve, but the computational requirements and analysis complexity increase
Solution Approach 1:
The patent segments the stress analysis into discrete, manageable components by evaluating each cell's stress contribution independently and combining these effects through superposition. The layout is divided into regions around each transistor, and stress effects are calculated for each region separately using pre-determined parameters, making the overall analysis more tractable while maintaining accuracy.
Solution Approach 2:
The patent transforms the complex physical stress field into simplified parameter representations that can be easily processed during placement. By converting continuous stress distributions into discrete stress effect parameters based on neighboring cell types and positions, the system maintains reliable performance prediction while reducing analysis complexity to levels suitable for automated placement tools.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of physical test fabrications required by 30-40%, significantly cutting costs and time to market for new IC technologies, while providing accurate performance evaluations and stress considerations in the design process.
Implementation Method 1
Intentional stresses and unintentional stresses in the layout, as well as unwanted variations in intentional stresses, affect the electrical properties of the transistor due to electronic band deformation of various materials used in integrated circuits and change in electron and hole mobility in transistors
Data Source
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AI summary
Disclosed is technology for placing cells in a circuit design layout to thereby improve the operation of place-and route equipment used for fabrication of an integrated circuit. The target cells are chosen from a cell library which includes descriptions for a plurality of cells, and information about dependency of each cell on hypothetical boundary conditions that can be imposed on the cell by any stress source originating in the vicinity of said cell in the layout. In order to select a cell for a target location in the layout, boundary conditions imposed on the target position by each of the cells neighboring the target position are determined. The system then selects an appropriate target cell in dependence upon the determined boundary conditions and the performance of the cell based on the boundary conditions imposed on the cell by the neighboring cells from the cell library.