Standard Cell Row Layout With Shared Power Lines and Nanosheet Matching
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Solution Overview
Problem
Existing semiconductor integrated circuit devices face challenges with increased off-current and power consumption due to excessive transistor scaling, and there is a need for a layout structure that includes standard cells with no logical function in semiconductor integrated circuits with varying cell row heights.
Innovation Solution
A layout structure for semiconductor integrated circuits with alternating cell rows of different heights, where standard cells with and without logical functions have nanosheets of equal width and position, and power lines are shared across rows to optimize performance and reduce manufacturing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If standard cells with no logical function are included in semiconductor integrated circuits with varying cell row heights, then layout flexibility and circuit termination capability are improved, but manufacturing precision and performance predictability deteriorate due to variations in nanosheet dimensions
Solution Approach 1:
The patent applies local quality by making the nanosheets in terminal cells (cells with no logical function) have the same width and position in the second direction as the nanosheets in adjacent standard cells with logical functions. This localized adjustment ensures that while terminal cells serve their termination purpose, their nanosheet dimensions remain consistent with functional cells, thereby maintaining manufacturing precision and performance predictability across the entire circuit block.
2Productivity
If transistor scaling is reduced to improve integration degree and operating speed, then device density increases, but off current increases and power consumption rises significantly
Solution Approach 1:
The patent addresses the power consumption issue by changing the physical parameters of the nanosheets - specifically making them greater in width in the second direction compared to conventional transistors. This parameter change increases the drive capability of the transistors, allowing them to operate efficiently at lower voltages and reducing off-current, thereby lowering overall power consumption while maintaining high integration density through the three-dimensional nanosheet structure.
Data Source
AI summary
In a semiconductor integrated circuit device, a plurality of cell rows each including standard cells arranged in the X direction are placed. The plurality of cell rows include a first cell row having a height H1 and a second cell row having a height H2 (H1<H2). The first cell row includes a logic cell and a cell having no logical function, and the second cell row includes a logic cell and a cell having no logical function. Nanosheets of the cells in the first cell row are smaller in width in the Y direction than nanosheets of the cells in the second cell row.