CEM Power Clamp Circuit for Accurate ESD Protection
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Solution Overview
Problem
Conventional power clamp circuits face challenges in accurately managing electrostatic discharge (ESD) due to large manufacturing tolerances in R-C circuit components, requiring increased current carrying capacity to prevent premature clamp transistor activation.
Innovation Solution
Incorporating Correlated Electron Material (CEM) devices that exhibit abrupt conductive/insulative state transitions, controlled by voltage and current, to form a power clamp circuit that reduces manufacturing variations and eliminates the need for additional capacitors, achieving a more accurate and compact ESD protection solution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional R-C circuit components are used in power clamp circuits, then the circuit can provide ESD protection, but large manufacturing tolerances cause inaccurate timing and require increased current carrying capacity
Solution Approach 1:
The patent replaces conventional R-C circuit components with a current-mode logic (CML) circuit that operates on different electrical parameters. The CML circuit uses differential voltage signals and current mirrors to achieve timing functionality, fundamentally changing the parameter domain from resistance-capacitance time constants to current-voltage differential operations, thereby eliminating sensitivity to R-C manufacturing tolerances
Solution Approach 2:
The patent substitutes the passive R-C timing mechanism with an active current-mode logic circuit that uses transistor-based current mirrors and differential amplification. This replacement transforms the timing mechanism from a passive component-dependent system to an active device-dependent system with controlled current paths, achieving precise timing without relying on passive component values
2Reliability
If current carrying capacity of clamp transistor is increased to accommodate smallest R-C values, then ESD protection is ensured, but device area and complexity increase
Solution Approach 1:
The CML circuit incorporates feedback mechanisms through differential signal paths and current mirrors that continuously monitor and adjust the timing signal. The differential structure provides inherent feedback where changes in one branch are compensated by the other, ensuring reliable ESD detection and response without requiring oversized transistors
Solution Approach 2:
The CML circuit performs multiple functions within a compact structure: it provides timing discrimination, signal amplification, and ESD detection simultaneously. The current mirrors serve both as signal transmission elements and as gain elements, eliminating the need for separate functional blocks that would increase device area
3Duration of action of moving object
If additional capacitors are used in conventional power clamp circuits, then timing functionality is achieved, but device area increases
Solution Approach 1:
The patent extracts and eliminates the capacitor element from the timing circuit by replacing the R-C time constant mechanism with a current-mode differential timing approach. The timing function is achieved through current charging/discharging paths and differential voltage comparisons rather than capacitive energy storage, removing the area-consuming capacitor components
Solution Approach 2:
The patent merges the timing function with the signal detection and amplification functions in a single integrated CML circuit structure. The differential pair simultaneously performs timing discrimination and signal processing, eliminating the need for separate RC timing network and signal conditioning stages that would occupy additional area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CEM-based power clamp circuit provides a more accurate and compact ESD protection with reduced manufacturing variations, allowing for a smaller transistor to effectively dissipate ESD pulses and maintaining high resistance values, thus enhancing the reliability and efficiency of ESD management.
Implementation Method 1
Correlated Electron Material (CEM) exhibits an abrupt conductive/insulative state transition arising from electron correlations in the material, rather than from solid state structural phase changes. The transition may be controlled by a voltage and current applied across the material.
Data Source
AI summary
A circuit is provided for limiting an applied voltage applied between a power line and an electrical ground. The circuit includes a transistive element connected between the power line and the electrical ground to provide a channel, where current flow through the channel is controlled by a control voltage provided to a control terminal of the transistive element. A first Correlated Electron Material (CEM) device having an impedance state is coupled between the power line and a first node, and a sensing circuit coupled between the first node and the control terminal of the transistive element. The sensing circuit is configured to detect a voltage drop across the CEM device and to provide the control voltage. The channel of the transistive element is opened when the detected voltage drop across the CEM device exceeds a threshold. The CEM device may contain a transition metal oxide (TMO), for example.