Center-Aligned PWM Circuit With Bidirectional Counting Resolution

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Solution Overview

Problem

The resolution of pulse width modulation signals in center-aligned mode is limited by its symmetrical characteristics, restricting the ability to increase resolution without modifying the overall circuit framework or increasing clock frequency, which can lead to higher dynamic power consumption and noise interference.

Innovation Solution

A pulse width modulation signal generation circuit and method utilizing a bidirectional counting mode, incorporating a clock generator, counting unit, and comparing unit, where the counting unit counts pulses based on a period parameter and outputs a middle value in two consecutive clock cycles when the parameter is odd, allowing for increased resolution without altering the clock frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the clock frequency is increased to improve the resolution of pulse width modulation in the center-aligned mode, then the resolution is improved, but the dynamic power consumption is higher and noise interference occurs

Engineering Contradiction:
Improveresolution of pulse width modulation signalVSAvoiddynamic power consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent changes the counting mode from unidirectional to bidirectional, allowing the counter to count both upward and downward. This parameter change in counting direction enables higher resolution PWM signals at the same clock frequency, avoiding the need to increase clock frequency and thus reducing power consumption and noise

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If the clock frequency is increased to improve the resolution of pulse width modulation in the center-aligned mode, then the resolution is improved, but the overall circuit framework needs to be significantly modified

Engineering Contradiction:
Improveresolution of pulse width modulation signalVSAvoidcircuit framework
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent modifies the counting operation parameter from unidirectional to bidirectional, which can be implemented through control logic that directs the counter to count up or down based on a direction signal. This parameter change achieves higher resolution without requiring significant modifications to the overall circuit framework, as the same counter hardware can be used with different counting directions

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If the clock frequency is increased to improve the resolution of pulse width modulation in the center-aligned mode, then the resolution is improved, but there may also be interference of noises

Engineering Contradiction:
Improveresolution of pulse width modulation signalVSAvoidnoise interference
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent changes the fundamental operating parameter from high-frequency unidirectional counting to lower-frequency bidirectional counting. By counting both upward and downward within the same period, the effective resolution is doubled without increasing the clock frequency, thereby avoiding the noise interference that would result from higher frequency operation

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9531367B2Pulse width modulation signal generation circuit and method
Publication Date: 2016.12.27 NUVOTON
  • US9531367B2 patent drawing
  • US9531367B2 patent drawing
  • US9531367B2 patent drawing

AI summary

A pulse width modulation signal generation circuit and a pulse width modulation signal generation method are provided. A clock generator is configured for generating a clock signal including a plurality of pulses. The counting unit is coupled to the clock generator, and configured for storing a period parameter and outputting a counting value by counting the pulses of the clock signal based on the period parameter and a bidirectional counting mode. The comparing unit is coupled to the counting unit and is configured for comparing the counting value and a comparing threshold to output a level control signal. The signal generating unit is coupled to the comparing unit and configured for generating a pulse width modulation signal according to the level control signal. When the period parameter is odd, the counting value outputted by the counting unit is equal to a middle value in the two continuous clock cycles.