Center Control Pads Reduce POP Package Thickness
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Solution Overview
Problem
Conventional semiconductor packages with Package On Package (POP) structures face challenges in reducing thickness and design complexity due to the conventional arrangement of control/address pads along the edge regions, which can lead to increased thickness and complexity in wiring paths.
Innovation Solution
The semiconductor package features control/address pads arranged in the center region of the substrate, separate from data pads, to reduce thickness and simplify wiring paths, with the data pads positioned in edge regions and substrate interconnection members arranged to connect the pads efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If control/address pads are arranged in edge regions like data pads, then the pad arrangement is uniform and simple, but the wiring path becomes complex and the package thickness increases
Solution Approach 1:
The patent inverts the conventional pad arrangement by placing control/address pads in the center region of the substrate while data pads remain in edge regions. This inversion simplifies the wiring path for control and address signals by reducing the distance they need to travel to reach the chip center, thereby reducing package thickness without significantly increasing arrangement complexity.
Solution Approach 2:
The patent applies different pad arrangement strategies to different regions of the substrate: data pads are positioned in edge regions to facilitate external connections, while control/address pads are positioned in the center region to minimize wiring path length. This localized optimization resolves the contradiction between uniform arrangement simplicity and wiring complexity.
2Length of stationary object
If control/address pads are arranged in the center region, then the wiring path is simplified and thickness is reduced, but the pad arrangement becomes more complex
Solution Approach 1:
By inverting the conventional approach and placing control/address pads in the center rather than edges, the patent achieves shorter wiring paths and reduced thickness. The increased arrangement complexity is acceptable because it provides significant benefits in signal integrity and package compactness.
3Device complexity
If all pads are arranged in edge regions, then the pad layout is uniform, but the wire interconnection length increases leading to increased thickness
Solution Approach 1:
The patent applies different arrangement strategies to different pad types based on their functional requirements: data pads in edge regions for external connectivity and control/address pads in the center for minimal signal path length. This localized differentiation reduces signal transmission time for critical control signals while maintaining overall layout organization.
Data Source
AI summary
A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate.