Center-Tapped Clock Transmission Circuit for Low-Jitter Signaling
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Solution Overview
Problem
High-speed clock transmission in semiconductor integrated circuits faces challenges with increased consumption current due to parasitic capacitance and susceptibility to noise, especially when using inductor peaking techniques, which also affect the duty ratio and band width.
Innovation Solution
A clock transmission circuit design that includes a first and second buffer, with an inductor unit connected between clock wirings, applying a common voltage to a center tap, allowing for stable clock transmission without high resistance elements, thereby reducing parasitic capacitance and noise susceptibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If inductor peaking technique is used for clock transmission, then consumption current is reduced, but susceptibility to external noise increases and jitter is caused
Solution Approach 1:
A common voltage generation circuit is introduced as an intermediary component to provide a stable reference voltage to the center tap of the inductor. This mediator circuit isolates the inductor from external noise while maintaining the low consumption current benefit of the inductor peaking technique.
Solution Approach 2:
The patent changes the voltage parameter by generating a dedicated common voltage through a separate circuit rather than using a fixed bias. This dynamic voltage adjustment reduces jitter caused by noise while preserving the energy efficiency of the inductor-based clock transmission.
2Object-affected harmful factors
If high resistance elements are used to provide bias, then influence on transmitted clocks is reduced, but parasitic capacitance increases and band is reduced
Solution Approach 1:
The common voltage generation circuit acts as an intermediary that provides bias without requiring high resistance elements in the signal path. This mediator approach reduces parasitic capacitance while still protecting the transmitted clocks from noise influence.
Solution Approach 2:
The patent replaces the traditional high resistance electrical element with an active voltage generation circuit. This substitution eliminates the parasitic capacitance associated with high resistance elements while maintaining the protective function against noise.
3Object-affected harmful factors
If impedance is increased to reduce noise influence, then noise susceptibility decreases, but jitter is caused and duty ratio deviates
Solution Approach 1:
The common voltage generation circuit dynamically adjusts the voltage parameter to compensate for impedance changes. This active regulation reduces jitter and prevents duty ratio deviation while still providing noise filtering benefits.
Solution Approach 2:
The patent implements feedback through the common voltage generation circuit that monitors and corrects for noise-induced variations. This feedback mechanism maintains reliable clock transmission by compensating for jitter and duty ratio deviations caused by impedance changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces consumption current, minimizes jitter and duty ratio deviation, and maintains stable high-speed clock transmission, even with increased impedance, by using a center-tapped inductor configuration and common voltage generation.
Implementation Method 1
an inductor is, for example, located in parallel with the load capacitance to generate parallel resonance, so that the impedance seen by the buffer of the clock transmission circuit is increased and clock transmission is performed by making the load capacitance appear to be low
Data Source
AI summary
A clock transmission circuit includes a first buffer, a second buffer, and an inductor unit. The first buffer is configured to receive a first clock which is one of differential clocks, and to buffer and output the first clock to a first clock wiring. The second buffer is configured to receive a second clock which is the other of the differential clocks, and to buffer and output the second clock to a second clock wiring. The inductor unit is connected between a first node of the first clock wiring and a second node of the second clock wiring, and configured to include a center tap to which a common voltage is applied.