Half-Bridge Power Module Layout for Compact High Current Rating
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Solution Overview
Problem
Conventional power semiconductor modules face challenges in achieving high current ratings while maintaining a limited size, with uneven current sharing during switching events and limited space for silicon chips, leading to performance limitations.
Innovation Solution
A power semiconductor module design featuring a base plate with distinct areas for power and control terminals in the center and power semiconductor devices in parallel lines on either side, allowing for efficient current sharing and increased active area, thus enhancing performance and current rating while minimizing space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power semiconductor devices are arranged in a conventional half-bridge configuration with DC+ and DC- terminals guided toward the center, then the module achieves basic functionality, but the current rating is limited and the module size increases
Solution Approach 1:
The base plate is divided into distinct functional areas: a central contact area for DC+ and DC- terminals, and lateral device areas for power semiconductor devices. This segmentation allows optimal placement of components, enabling high current rating while maintaining compact size by eliminating wasted space in conventional center-guided configurations
Solution Approach 2:
The invention transitions from a conventional center-focused layout to a lateral distribution layout where devices are arranged in parallel lines on the sides of the base plate. This dimensional reorganization maximizes the use of available base plate area, increasing the active area for silicon chips without expanding the overall module footprint
2Power
If multiple power semiconductor devices are paralleled to increase current rating, then the current capacity increases, but current sharing becomes uneven during switching events
Solution Approach 1:
The base plate provides locally optimized electrical connection paths to each power semiconductor device through the contact area. This local quality control ensures that each device in the parallel configuration has equivalent and optimized current paths, achieving uniform current sharing during switching events while maintaining high overall current rating
3Power
If the active area for silicon chips is increased to improve performance, then the current rating increases, but the module size becomes larger
Solution Approach 1:
The invention reorganizes the layout from a center-focused arrangement to a lateral distribution arrangement where devices are positioned in parallel lines along the sides of the base plate. This dimensional change maximizes the utilization of the base plate area, increasing the active area for silicon chips without proportionally increasing the overall module size
Solution Approach 2:
By segmenting the base plate into contact area and device areas, the invention creates dedicated zones that optimize space utilization. This segmentation allows the device areas to be positioned efficiently along the lateral edges, maximizing the active area for power semiconductor devices within a compact footprint
Data Source
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AI summary
Power semiconductor module, comprising a base plate (12) with at least one substrate (11, 13, 15, 17) located on said base plate (12), wherein an electronic circuit is provided on said at least one substrate (11, 13, 15, 17), wherein located on the at least one substrate (11, 13, 15, 17) are electrical connectors comprising a DC+ power terminal (14), a DC- power terminal (16) and an AC power terminal (18) and further a control connector, wherein the power semiconductor module (10) is designed as a half-bridge module comprising a first amount (24) of switching power semiconductor devices (26, 28) and a second amount (30) of switching power semiconductor devices (32, 34), characterized in that the base plate (12) comprises a contact area (36), a first device area (38) and a second device area (40), wherein the contact area (36) is positioned in a center of the base plate (12) such, that the first device area (38) is positioned at a first side of the contact area (36) and that the second device area (40) is positioned at a second side of the contact area (36), the second side being arranged opposite to the first side, wherein the DC+ power terminal (14), the DC-power terminal (16), the AC power terminal (18) and the control connector are positioned in the contact area (36), wherein the first amount (24) of switching power semiconductor devices (26, 28) is positioned in the first device area (38) and wherein the second amount (30) of switching power semiconductor devices (32, 34) is positioned in the second device area (40), wherein all the power semiconductor devices (28, 30) in the first device area (38) are located in two parallel lines (42, 44) being aligned parallel to the width of the base plate (12) and wherein all the power semiconductor devices (32, 34) in the second device area (40) are located in two parallel lines (46, 48) being aligned parallel to the width of the base plate (12).