Central Buffer Switch Fabric with Scoreboard Coordination
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Solution Overview
Problem
Current packet routing in computer networks faces challenges in reducing latency and efficiently managing packet transmission through switch fabrics, particularly in scenarios where traffic bypasses the shared memory due to congestion, leading to suboptimal performance in high-speed networks.
Innovation Solution
The implementation of a method that utilizes a central buffer with a scoreboard system to manage packet transmission, where ingress writers and egress readers coordinate through packet identifiers and cell counts to ensure efficient transfer of packets without consulting the scoreboard when necessary, thereby reducing latency and optimizing packet forwarding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traffic is routed through shared memory in the switch fabric, then packet transmission can be handled with simple routing, but latency increases and performance deteriorates in high-speed networks
Solution Approach 1:
The patent segments the switch fabric into multiple independent fabric planes, each capable of handling traffic independently. This segmentation allows parallel processing of multiple packets simultaneously, increasing overall transmission speed and reducing latency by avoiding sequential access to shared memory resources.
Solution Approach 2:
The patent implements preliminary action through pre-allocation of buffer resources and pre-computation of routing paths. By preparing routing information and buffer allocations in advance, the system minimizes on-the-fly decision-making delays, thereby reducing latency while maintaining high transmission speeds.
2Reliability
If a centralized scoreboard system is used to manage packet transmission coordination, then synchronization between ingress writers and egress readers is achieved, but device complexity increases
Solution Approach 1:
The patent extracts the coordination function from a centralized scoreboard and distributes it to individual fabric planes and buffer modules. Each fabric plane maintains its own local state information, eliminating the need for a complex centralized scoreboard while preserving synchronization reliability through distributed coordination protocols.
Solution Approach 2:
The patent implements self-service by enabling each fabric plane and buffer module to autonomously manage its own state and coordination requirements. Modules independently track packet transmission states and make local decisions, reducing reliance on complex centralized control while maintaining synchronization through standardized interfaces and protocols.
3Productivity
If multiple fabric planes are implemented to increase bandwidth, then packet transmission capacity improves, but device complexity and resource requirements increase
Solution Approach 1:
The patent merges multiple fabric planes into a unified architectural framework with standardized control mechanisms. By combining resource management, routing logic, and state tracking into shared components that serve all fabric planes, the system increases transmission capacity while minimizing the complexity increment through economies of scale and resource sharing.
Data Source
AI summary
A system and method of transferring cells through a router includes writing one or more of the plurality of cells, including a first cell, of a packet from an ingress stream of an ingress writer to a central buffer, storing a packet identifier entry in the first egress reader scoreboard in each of the plurality of egress readers, the packet identifier entry including a packet identifier, a valid bit, a hit bit and a write cell count, wherein the valid bit is configured to indicate that the packet identifier entry is valid, the hit bit is configured to indicate that no cells in the packet have been read from the central buffer and the write cell count equals the number of cells in the packet written to the central buffer, and reading the packet from the central buffer as a function of the packet identifier entry.