Central Mode Control Logic for Cipher Hardware Modules
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Solution Overview
Problem
Existing security protocols require support for multiple independent cipher modes of operation, which is challenging to implement efficiently in software and lacks efficient hardware-based solutions for secure communication in wireless networks.
Innovation Solution
A semiconductor device with central mode control logic and multiple cipher hardware modules that can implement various cipher modes such as CBC, CTR, CCM, and OCB, allowing for flexible and efficient encryption and decryption operations across different protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple cipher modes are implemented in software, then protocol compatibility is improved, but processing efficiency deteriorates
Solution Approach 1:
The patent divides the encryption system into separate hardware modules for different cipher modes (CBC mode module, CTR mode module, CCM mode module, OCB mode module), each dedicated to a specific mode of operation. This segmentation allows each module to be optimized for its specific function while maintaining overall system versatility across multiple protocols.
Solution Approach 2:
The patent implements a universal hardware architecture where multiple independent cipher mode modules share common resources such as the key schedule generation unit, counter increment unit, and data processing units. This multi-functionality approach enables efficient processing of different cipher modes without requiring completely separate hardware implementations for each mode.
2Productivity
If multiple cipher modes are implemented in hardware, then processing efficiency is improved, but device complexity increases
Solution Approach 1:
The patent merges common functional components across different cipher mode modules, including the key schedule generation unit, counter increment unit, and data processing units. By combining these shared resources, the patent reduces redundant hardware while maintaining the ability to efficiently process multiple cipher modes simultaneously.
Solution Approach 2:
The patent creates a universal hardware platform where different cipher mode modules can share common infrastructure such as the mode control logic, data buffering mechanisms, and output processing units. This universality reduces the overall hardware footprint while preserving the efficiency benefits of dedicated hardware implementations.
3Adaptability or versatility
If redundant logic is used to support multiple cipher modes, then protocol support is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines common functional logic across different cipher mode implementations, particularly in the key schedule generation and data processing units. This merging eliminates redundant circuitry that would otherwise be required if each cipher mode had completely independent hardware implementations, thereby reducing manufacturing costs.
Solution Approach 2:
The patent implements universal hardware components that can serve multiple cipher modes, such as a common key schedule generation unit and shared data processing logic. This approach reduces the total number of unique circuit components that need to be manufactured, lowering production costs while maintaining broad protocol support.
Data Source
AI summary
The present disclosure relates generally to semiconductor devices and related methods of operation. A semiconductor device is disclosed that comprises at least one cipher interface (126, 128) to a plurality of different cipher hardware modules (112, 114, 116) and central mode control logic (130-138, 106) responsive to the at least one cipher interface (126, 128). The central mode control logic (130-138, 106) is configured to provide a cipher operation in accordance with a selected cipher mode (104) in connection with at least one of the plurality of different cipher hardware modules (112, 114, 116).