Central Processor Task Execution via Pre-calculated Subsystem Timing

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Solution Overview

Problem

Current systems managing tasks by a central processor in real-time operating systems face challenges such as high response time requirements, complex integration, insufficient memory, and difficulty in managing multimedia functions like pause and fast forward, especially in multimedia applications, leading to disrupted data processing and synchronization issues.

Innovation Solution

A method and system for processing concurrent tasks using a central processor and a subsystem, where tasks are composed of messages with subtask parameters and links indicating processing times, utilizing counters and semaphores to manage access and execution, reducing the need for processor intervention and improving timing precision.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the central processor manages task execution by sending subtasks and waiting for responses, then the subsystem can be controlled, but the response time requirement becomes extremely short and integration becomes difficult

Engineering Contradiction:
Improvetask execution controlVSAvoidresponse time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing execution times for multiple subtasks in advance. Instead of calculating execution time when a subtask is sent, the system pre-computes execution times for sequences of subtasks and stores them in a look-up table, allowing the subsystem to execute tasks without waiting for processor responses.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary mechanism in the form of a look-up table that stores pre-calculated execution times. This intermediary allows the subsystem to obtain execution time information without direct real-time communication with the processor, decoupling the tight response time requirement from the control loop.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the central processor manages all task coordination and memory access, then task execution can be controlled, but the processor memory becomes insufficient and data may be erased

Engineering Contradiction:
Improvetask coordinationVSAvoidprocessor memory
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts the execution time calculation function from the central processor and stores it in a separate look-up table. This extraction removes the burden of real-time calculation from the processor memory, allowing the system to handle larger task sequences without increasing processor memory requirements.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

By pre-calculating and storing execution times in advance, the system eliminates the need for the processor to maintain large amounts of runtime data in memory. The pre-computed values are stored once and reused, significantly reducing the memory burden on the processor during task execution.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the processor sends subtasks sequentially with response waiting, then task execution can be monitored, but the precision in timing of subtasks by the subsystem is insufficient

Engineering Contradiction:
Improvetask execution monitoringVSAvoidsubtask timing precision
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent pre-calculates execution times for subtasks and stores them in a look-up table before execution. This allows the subsystem to execute subtasks with precise timing based on pre-determined values, eliminating timing errors that would accumulate with sequential processor monitoring.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The subsystem uses the pre-stored execution time information to self-regulate its task execution timing without continuous processor intervention. The subsystem can independently determine when to execute each subtask based on the pre-calculated timing information, achieving precise timing autonomously.

Inventive Principle:
Principle #25Self-service

4Reliability

If the central processor manages all responses from the subsystem, then task execution can be controlled, but other tasks by the processor are slowed down

Engineering Contradiction:
Improvesubsystem response controlVSAvoidprocessor task execution speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the response management function from the central processor by pre-calculating execution times and storing them in a look-up table. This allows the subsystem to operate more independently, reducing the processor's involvement in response handling and freeing the processor to execute other tasks more efficiently.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

By pre-calculating and storing execution times before task execution, the system eliminates the need for the processor to handle responses in real-time. The processor only needs to initiate tasks, while the subsystem autonomously manages execution timing based on pre-computed values, significantly improving processor productivity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7797700B2Method of executing concurrent tasks by a subsystem managed by a central processor
Publication Date: 2010.09.14 STMICROELECTRONICS FRANCE
  • US7797700B2 patent drawing
  • US7797700B2 patent drawing
  • US7797700B2 patent drawing

AI summary

Systems and methods are provided for processing different concurrent tasks by a subsystem managed by a central processor. Each tasks is comprised of successive messages including a first message, intermediate messages, and a last message. Each intermediate message comprises a subtask parameter and a link to the next message that indicates the time when the next message is to be processed. The central processor and the subsystem are connected to a storage memory and several counters associated with respective tasks. The system and method reduce task disruptions of the system.