Central Row Decoder Architecture for Adaptive Memory Erasing
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Solution Overview
Problem
Conventional memory systems face reliability issues due to defects in memory devices, leading to inefficiencies and increased power consumption, especially when using system management for partially good blocks with single edge row decoders, which cause interference and require adjustments in read levels.
Innovation Solution
Implementing a memory device architecture with a central row decoder within the page, providing physical isolation and reducing interference, allowing for adaptive erasing of partially good blocks by determining which portions to erase based on memory addresses, thus reducing energy consumption and operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single edge row decoder is used for memory management, then the device complexity is reduced, but interference between blocks increases and read level adjustments are required
Solution Approach 1:
The memory block is divided into two independent halves, each managed by its own row decoder. This segmentation allows independent control of each half, eliminating interference between blocks while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
A dual row decoder configuration acts as an intermediary structure between the memory blocks and control logic. The two row decoders work in parallel to independently manage different halves of the memory, providing isolation and eliminating the need for read level adjustments while maintaining system controllability.
2Productivity
If adaptive erasing of partially good blocks is implemented, then productivity is improved, but device complexity increases
Solution Approach 1:
The memory block is segmented into two independently erasable halves, each controlled by its own row decoder. This allows selective erasing of only the defective half while preserving the good half, improving productivity by avoiding unnecessary erasure operations while keeping the control mechanism relatively simple through the existing dual decoder architecture.
Solution Approach 2:
Instead of erasing the entire block or no block at all, the system performs partial erasing by targeting only the specific half that requires it. This partial action approach improves productivity by minimizing data loss and operation time while the dual row decoder structure keeps the implementation complexity manageable.
Data Source
AI summary
Methods, systems, and apparatuses include receiving, from a host system, an erase command for a memory device. A portion of memory of the memory device is determined using an address of the erase command. It is determined to include a first subportion of the portion of memory in an erase operation and to exclude a second subportion of the portion of memory in the erase operation. Trim settings are selected in response to the determination to include the first subportion and exclude the second subportion. The erase operation is executed on the first subportion but not the second subportion based on the trim settings.