Central Row Decoder Layout for Fast Non-Volatile Memory Word Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing non-volatile memory architectures face challenges in achieving high speed, low area, and low power consumption due to constraints imposed by the distribution of row decoders at the tile level and the use of limited transistor types, which require different voltage domains for read and write operations.
Innovation Solution
A row decoder architecture that utilizes a central row decoder and buffer circuits with MOS transistors operating at different voltage levels, combined with level-shifted signals, to efficiently drive word lines while minimizing power consumption and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If row decoders are distributed at the tile level, then the driving capability for fast word line selection is improved, but the area occupied by decoder circuits increases and power consumption rises
Solution Approach 1:
The patent merges multiple distributed row decoders into a single centralized row decoder located outside the memory array. This consolidation reduces the total area occupied by decoder circuits while maintaining fast word line selection through efficient signal distribution to the memory tiles.
Solution Approach 2:
The patent segments the decoder functionality by separating the main decoding logic from the word line driving function. The centralized row decoder generates decode signals that are then distributed to individual memory tiles, where local buffer circuits complete the word line selection. This segmentation allows area reduction while preserving speed.
2Adaptability or versatility
If two different voltage domains are used for read and write operations, then the operational flexibility is improved, but the device complexity increases due to multiple transistor types
Solution Approach 1:
The patent changes the voltage parameter dynamically through a voltage selector circuit that switches between first voltage (read mode) and second voltage (write mode) based on the operation type. This allows the same transistor type to operate in different voltage domains, reducing device complexity while maintaining operational flexibility.
Solution Approach 2:
The patent introduces dynamic voltage control where the voltage supplied to the transistor varies according to the operational mode. A control signal determines whether the transistor operates at first voltage or second voltage, enabling adaptive performance optimization without requiring multiple fixed-voltage transistor types.
3Speed
If high driving voltage is applied during write operations, then the writing speed is improved, but the power consumption increases
Solution Approach 1:
The patent employs periodic voltage switching where high second voltage is applied only during write operations and low first voltage is used during read operations. This periodic modulation of voltage based on operational phase allows high writing speed when needed while minimizing power consumption during normal read operations.
Solution Approach 2:
The patent applies excessive voltage (second voltage higher than first voltage) only partially - specifically during write operations when high current is needed. During read operations, the lower first voltage suffices, avoiding unnecessary power consumption while maintaining adequate read performance.
4Area of stationary object
If a centralized row decoder is used, then the area is reduced, but the signal distribution complexity increases
Solution Approach 1:
The patent resolves signal distribution complexity by organizing memory tiles in a two-dimensional array and distributing decode signals systematically across rows and columns. This spatial organization transforms the complexity from an unmanageable many-to-many connection into a structured grid-based distribution pattern that is easier to implement and route.
Data Source
AI summary
In a non-volatile memory device, a memory sector is provided. The memory sector includes a plurality of tiles arranged horizontally. Each tile includes a plurality of memory cells arranged in horizontal word lines and vertical bit lines. A pre-decoder is configured to receive a set of encoded address signals to produce pre-decoding signals. A central row decoder is arranged in line with the plurality of tiles, receives the pre-decoding signals and produces level-shifted pull-up and pull-down driving signals for driving the word lines. First buffer circuits are arranged on a first side of each tile. Each of the first buffer circuits is coupled to a respective word line, receives a level-shifted pull-up driving signal and a level-shifted pull-down driving signal, and selectively pulls up or pulls down the respective word line as a function of the values of the received signals.