IC Substrate Central Stacking for Fine-Pitch Reliable Integration
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Solution Overview
Problem
Conventional approaches face challenges in forming compact and reliable integrated circuit substrates with high functionality and small pitch, which are essential for supporting increasingly powerful and miniaturized components under harsh conditions.
Innovation Solution
The integration of a central section with vertically stacked functional volume sections on an integrated circuit substrate, allowing for a pitch of not more than 150 µm, enables a compact and flexible design with enhanced mechanical and electrical reliability, incorporating various functionalities such as power management, security, thermal management, and electro-optical functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional approaches are used to form component carriers, then manufacturing simplicity is maintained, but pitch cannot be reduced below conventional limits and functionality is limited
Solution Approach 1:
The patent transitions from conventional two-dimensional planar substrate design to a three-dimensional vertically stacked architecture. Multiple functional layers (logic layer, memory layer, I/O layer) are stacked vertically with interconnect structures connecting them, enabling high-density integration and reduced pitch while maintaining manufacturability through standardized stacking processes.
Solution Approach 2:
The substrate is divided into distinct functional segments or layers, each performing specific functions (logic operations, memory storage, I/O operations). This segmentation allows independent optimization of each layer's pitch and layout, enabling overall pitch reduction while maintaining manufacturing simplicity through modular assembly of pre-fabricated layers.
2Manufacturing precision
If pitch is reduced to increase component density, then integration density improves, but mechanical robustness and electrical reliability deteriorate
Solution Approach 1:
The patent employs composite interconnect structures combining multiple materials with complementary properties. Conductive interconnects use copper or tungsten for low resistance, surrounded by barrier layers and embedded in low-k dielectric materials. This composite approach maintains electrical reliability at reduced pitch by controlling signal integrity, impedance, and Crosstalk through material selection and structural design.
Solution Approach 2:
The design incorporates redundancy and error correction mechanisms built into the substrate architecture before failures can occur. Multiple interconnect paths, redundant logic elements, and built-in self-test structures are integrated to detect and correct errors, ensuring electrical reliability even as pitch decreases and manufacturing variations increase.
3Manufacturing precision
If pitch is reduced to support miniaturized components, then component density increases, but mechanical robustness under harsh conditions deteriorates
Solution Approach 1:
The substrate uses composite material systems combining ceramic substrates (for mechanical strength and thermal stability) with organic dielectric layers (for fine-pitch routing). The ceramic core provides mechanical robustness under harsh conditions, while the organic layers enable reduced pitch through flexible patterning. This composite structure maintains both mechanical strength and high integration density.
Solution Approach 2:
By moving to three-dimensional vertical stacking, the patent reduces the lateral footprint and pitch requirements while maintaining or increasing overall mechanical strength through the vertical arrangement of multiple supported layers. The vertical architecture distributes mechanical stresses across multiple interfaces and layers, enhancing overall structural robustness despite reduced lateral dimensions.
Data Source
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AI summary
An integrated circuit substrate (100) for surface mounting an integrated circuit component (102) thereon, wherein the integrated circuit substrate (100) comprises a central section (104), and at least two vertically stacked functional volume sections (106) in the central section (104), wherein a pitch (D) at an integrated circuit component mounting side (108) of the integrated circuit substrate (100) is not more than 150 µm.