Centralized di/dt Manager for SoC Clock Gating Noise
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Solution Overview
Problem
Clock gating in modern SoCs leads to significant di/dt noise due to sudden changes in current requirements, which can result in power supply noise and limit power-saving opportunities, especially in high-performance chips with multiple CPU cores.
Innovation Solution
A centralized di/dt manager is introduced to receive and manage clock gating requests from multiple computing devices, determining which requests to approve to keep the total clock gating value within a threshold, thereby controlling di/dt noise and reducing noise margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock gating is performed on multiple components to save power, then power consumption is reduced, but di/dt noise increases causing power supply noise
Solution Approach 1:
The patent applies preliminary action by predicting future clock gating requests before they occur. The prediction unit forecasts which components will need clock gating in upcoming time windows, allowing the system to prepare and manage di/dt noise proactively. This enables power saving opportunities to be identified and executed while controlling noise through advance planning of clock gating operations.
Solution Approach 2:
The patent introduces an intermediary management unit that acts as a mediator between power saving requirements and noise control. This unit coordinates clock gating requests, manages the timing of clock pulse removal, and balances power consumption reduction with di/dt noise control. The intermediary orchestrates the interaction between multiple components to achieve both power efficiency and noise management.
2Object-affected harmful factors
If a large amount of noise margin is allocated to mitigate di/dt effect, then di/dt noise is controlled, but power-saving opportunities are reduced and system operates at lower speed
Solution Approach 1:
The patent applies dynamics by making noise margin allocation flexible and adaptive rather than static. The system dynamically adjusts noise margins based on predicted clock gating patterns and actual di/dt noise conditions. This allows the system to use minimal noise margins when needed, maximizing power-saving opportunities and maintaining higher operating speeds while still controlling di/dt noise effectively when necessary.
Solution Approach 2:
The patent changes the parameter of noise margin allocation from a fixed value to a variable that adapts to system conditions. By monitoring predicted clock gating requests and actual di/dt noise levels, the system adjusts noise margins in real-time, allowing it to operate at higher speeds with reduced margins when safe, and increase margins only when di/dt noise control is critical.
3Object-affected harmful factors
If staggering is used for clock gating of multiple components, then di/dt effect is mitigated, but it cannot help when complex fine-grained clock gating is happening inside components
Solution Approach 1:
The patent applies segmentation by dividing clock gating management into hierarchical levels: component-level fine-grained clock gating within individual components, and system-level coordinated management across multiple components. The prediction unit segments the analysis of clock gating requests by component and time window, allowing detailed control within components while coordinating noise management across the system. This segmented approach enables both fine-grained internal clock gating and staggered external coordination.
Solution Approach 2:
The patent introduces an intermediary prediction unit that mediates between fine-grained component-level clock gating requests and system-level noise control. This intermediary receives detailed clock gating requests from individual components, predicts their combined di/dt noise impact, and coordinates the timing to mitigate noise while preserving the flexibility of fine-grained clock gating within each component.
Data Source
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AI summary
Methods, systems, and apparatus, for di/dt management during clock gating. One of the apparatus includes a plurality of computing devices, wherein each computing device has respective clock gating logic that is configured to apply clock gating to a portion of the computing device; and a centralized di/dt manager that is configured to perform operations including: receiving, from the plurality of computing devices, respective clock gating requests to perform the clock gating, wherein each clock gating request specifies a respective clock gating value representing how much of the requesting computing device will be clock gated, computing, from the clock gating requests, a total clock gating value of the device, determining, from the total clock gating value, which of the clock gating requests to approve, and providing, the each of the plurality of computing devices, responses to the respective clock gating requests, each response representing whether the clock gating request is approved.