Centralized DLL Synchronization for Stacked Semiconductor Chips
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with multiple stacked chips, existing configurations either consume excessive power due to independent synchronization of data and clock signals on each chip or fail to synchronize data signals with the clock signal on the control chip, limiting high-speed data transmission.
Innovation Solution
A semiconductor device configuration where a control chip synchronizes data signals from controlled chips using a synchronization signal, delayed synchronization signal, and replica signal, with a phase comparator circuit to adjust the delay, ensuring all data signals are synchronized with the clock signal, reducing power consumption and enhancing data transmission speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a DLL circuit is mounted on each chip for independent synchronization, then data and clock signals can be synchronized in each chip, but power consumption increases significantly
Solution Approach 1:
The patent merges the synchronization function from multiple distributed DLL circuits into a single centralized DLL circuit located on the control chip. This single DLL generates the clock signal that is distributed to all controlled chips, eliminating the need for separate DLL circuits on each chip while maintaining synchronization accuracy across the entire system.
Solution Approach 2:
The patent introduces a delay circuit as an intermediary component between the clock signal generation and the data transmission. This delay circuit adjusts the phase of the clock signal to compensate for transmission delays, ensuring that data signals arrive synchronized with the clock signal at the control chip without requiring additional DLL circuits on each controlled chip.
2Use of energy by moving object
If data signals are transmitted from controlled chips to control chip without synchronization processing, then power consumption is reduced, but data transmission speed is limited due to lack of synchronization
Solution Approach 1:
The patent extracts the synchronization processing function from the controlled chips and relocates it to the control chip. The controlled chips simply transmit data signals without performing synchronization operations, while the control chip handles all synchronization processing including phase comparison and delay adjustment, thereby reducing power consumption on controlled chips while maintaining high-speed data transmission capability.
Data Source
AI summary
A semiconductor device includes a first controlled chip and a control chip stacked therewith. The first controlled chip includes a first circuit outputting a data signal in response to a synchronization signal, an input/output circuit outputting the data signal to a data terminal in synchronization with a delayed synchronization signal, and a replica circuit replicating an output circuit and outputting a replica signal to a first replica terminal in synchronization with the delayed synchronization signal. The control chip includes a first control circuit outputting a synchronization signal and receiving a data signal, a delay adjustment circuit delaying the synchronization signal and outputting the same as a delayed synchronization signal, a phase comparator circuit comparing the phases of the replica signal and the synchronization signal, and a delay control circuit controlling the delay amount of the delay adjustment circuit based on a comparison result of the phase comparator circuit.