Centralized ECC Circuit Layout for Higher Volatile Memory Capacity
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Solution Overview
Problem
Incorporating error correction circuits (ECC) on memory dies reduces the capacity of volatile memory due to area constraints, leading to inefficiencies in data communication and increased power consumption.
Innovation Solution
Implementing a centralized ECC circuit on the memory controller die instead of the memory die, allowing for faster error correction and reducing latency and power consumption while increasing volatile memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction circuits are incorporated on memory dies, then data reliability is improved, but volatile memory capacity is reduced due to area constraints
Solution Approach 1:
The ECC circuit is extracted from the memory die and relocated to the memory controller die. This separation removes the ECC circuit from the constrained memory die area, allowing full utilization of the memory die for storage capacity while maintaining error correction functionality in the controller where area constraints are less critical.
2Reliability
If error correction circuits are incorporated on memory dies, then data reliability is improved, but power consumption is increased
Solution Approach 1:
The ECC circuit is extracted from the memory die and placed in the memory controller die. This relocation reduces power consumption by eliminating redundant ECC functionality that would otherwise be distributed across multiple memory dies, consolidating error correction operations in a single centralized location that can manage power more efficiently.
3Reliability
If error correction circuits are incorporated on memory dies, then data reliability is improved, but data communication efficiency is reduced
Solution Approach 1:
The ECC circuit is extracted from the memory die and centralized in the memory controller die. This eliminates the need for data to be transferred back and forth between memory die and ECC circuit on the same die, reducing communication latency and improving overall data communication efficiency while maintaining error correction capabilities.
Data Source
AI summary
Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.