Centralized ECC Placement for Multi-Channel Storage Reliability
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Solution Overview
Problem
Multi-channel mass storage devices face limitations in error correction due to single-channel ECC schemes, where the check bytes are tied to a specific sector size and ECC algorithm strength, which is not adaptable for diverse storage devices and sector sizes.
Innovation Solution
A centralized ECC engine that generates and manages check bytes independently of individual storage channels, allowing for flexible sector sizes and ECC algorithm strengths, protecting data across all channels and buffer memory, and decoupling check bytes from storage element limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If per-channel ECC scheme is used, then error correction is provided for each storage device, but the check bytes are tied to specific sector size and ECC algorithm strength which limits adaptability
Solution Approach 1:
The patent combines multiple per-channel ECC controllers into a single shared ECC controller that serves all storage devices. This shared controller maintains multiple independent ECC engines that can be dynamically allocated to different channels, allowing the system to provide error correction for multiple devices while using a unified control structure that enables flexible configuration of sector sizes and ECC algorithm strengths across different storage types.
Solution Approach 2:
The shared ECC controller is designed with multi-functionality to handle diverse storage devices with different sector sizes and ECC requirements. It incorporates multiple ECC engines that can be configured with different parameters (sector sizes, ECC strengths, algorithms) to accommodate various storage device types, making the system universally applicable rather than dedicated to a single configuration.
2Reliability
If per-channel ECC scheme is used, then error correction is provided for each channel, but the controller chip size and cost increase
Solution Approach 1:
The patent merges multiple ECC controllers into a single shared controller unit that contains multiple ECC engines. This consolidation reduces the overall controller chip size by eliminating redundant control logic, registers, and support circuitry that would exist in separate per-channel controllers, while still providing error correction capabilities for all storage devices through the shared engine pool.
Solution Approach 2:
The shared ECC controller performs multiple functions by dynamically allocating its ECC engines to different channels based on demand. This multi-functional design allows a single controller to replace what would otherwise require multiple dedicated controllers, reducing chip size and cost while maintaining comprehensive error correction across all storage devices.
3Reliability
If per-channel ECC scheme is used, then error correction is provided just before data is written, but the ECC algorithm strength is limited by the size of designated location for storing check bytes
Solution Approach 1:
The shared ECC controller incorporates multiple ECC engines that can be configured with different algorithm strengths and types. This universal design allows the system to select and apply the appropriate ECC strength for each storage device based on its requirements, rather than being constrained by a fixed check byte location size. The controller can dynamically adjust ECC parameters to match the specific needs of different storage devices.
Solution Approach 2:
The patent enables parameter changes in the ECC configuration by allowing the shared controller to dynamically adjust check byte sizes, ECC algorithm types, and correction strengths based on the specific requirements of different storage devices. This flexibility is achieved through the shared controller's ability to reconfigure its ECC engines for different operating conditions and device types.
Data Source
AI summary
A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels.