Centralized Memory Protection for SoC Bus Access Control
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Solution Overview
Problem
Current microprocessor architectures lack comprehensive protection for memory and peripherals across all potential master devices and memory destinations, leading to inconsistent and decentralized protection schemes that fail to ensure secure and controlled memory access, especially in system-on-chip (SoC) devices.
Innovation Solution
A centralized memory protection function (CMP) is introduced to manage and enforce access rights for all bus data transfers within the SoC, ensuring that all memory and peripheral accesses are checked against predefined settings, preventing unauthorized access by raising error flags or aborting bus transfers, and providing a single point of control for coherent settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If decentralized protection units (MMU/MPU) are used for each master device, then each device can independently control its memory access, but the protection settings become incoherent and inconsistent across the system
Solution Approach 1:
The patent introduces a centralized memory protection unit that acts as an intermediary between master devices and memory destinations. This central unit receives and validates access requests from all masters, ensuring coherent protection settings across the entire system while maintaining the ability to control individual device access patterns.
Solution Approach 2:
The patent consolidates multiple distributed protection functions into a single centralized memory protection unit. By merging the protection capabilities of individual MMU/MPU units into one centralized authority, the system achieves consistent and coherent protection settings across all master devices and memory destinations.
2Reliability
If MMU is used for memory protection, then CPU core accesses are protected, but the protection granularity is too coarse (page-based) for embedded applications
Solution Approach 1:
The patent changes the granularity parameter of memory protection from page-based (coarse) to byte-based or word-based (fine). The centralized memory protection unit can define protection regions with precise address ranges and granular access permissions, enabling fine-grained control suitable for embedded applications while maintaining CPU protection.
3Ease of operation
If multiple distributed protection settings are allowed, then each master device can be configured independently, but conflicting settings occur due to the distributed nature of the configuration
Solution Approach 1:
The centralized memory protection unit serves as an intermediary that receives configuration requests from multiple master devices and ensures that settings are consistent across the system. It manages the configuration space to prevent conflicts while allowing independent configuration of each device's access patterns.
Solution Approach 2:
The patent implements feedback mechanisms where the centralized protection unit validates access requests and configuration settings against established rules. When conflicts are detected, the system can provide feedback to the initiating device or automatically resolve the conflict, ensuring configuration consistency across all devices.
4Device complexity
If no centralized protection is implemented, then device complexity is reduced, but comprehensive memory protection across all masters and destinations is lost
Solution Approach 1:
The centralized memory protection unit is designed to handle protection for all master devices and memory destinations within a single unified structure. This universal protection mechanism provides comprehensive coverage across the entire memory map while maintaining a relatively simple device structure compared to having multiple distributed protection units.
Data Source
AI summary
A system comprises one or more slave elements operably coupled to a plurality of master devices. A central protection function is operably coupled to a first communication bus and configured to control data flow between the one or more slave elements and the plurality of master devices via the communication bus.