Centralized Memory Repair Block for High-Density Cache
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Solution Overview
Problem
Conventional redundancy approaches in memory circuits add significant overhead and cost to address bit failures across large memory arrays, particularly in high-end microprocessors with high-density memory cells, where single bit failures become critical due to scaling and process variation.
Innovation Solution
Implementing a centralized redundancy block repair system that includes a repair memory array, comparison logic circuit, and multiplexer to identify and replace defective bitcells with redundant ones, supporting bank-interleaved access for single-cycle throughput and row/column repair, thereby reducing latency and overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional redundancy approaches are added in each sub-array to address bit failures, then manufacturing yield is maintained, but overhead and cost increase significantly
Solution Approach 1:
Multiple redundancy resources (row repair, column repair, and duplicated block repair) are merged into a single centralized repair block that shares common control logic and multiplexing infrastructure, reducing overall overhead while maintaining comprehensive repair capability across all sub-arrays
Solution Approach 2:
The centralized repair block is designed as a universal repair unit that can handle multiple types of repairs (row, column, and block-level) through a single infrastructure, eliminating the need for separate redundancy mechanisms in each sub-array and reducing total overhead
2Productivity
If duplicated block repair uses multiple instantiations to meet throughput requirements, then single-cycle throughput is achieved, but device complexity and area overhead increase
Solution Approach 1:
The memory system is divided into multiple banks that can be accessed in parallel, while a single centralized repair block serves all banks through time-multiplexed access. This segmentation allows throughput requirements to be met through parallel bank access rather than requiring multiple repair block instantiations
Solution Approach 2:
The centralized repair block dynamically switches between serving different banks using multiplexing controlled by bank select signals. The repair block adapts its operation based on which bank requires repair, enabling a single unit to handle multiple banks sequentially without sacrificing overall throughput
3Area of stationary object
If high-density memory cells with long self-bitline structures are used to increase compactness, then area efficiency improves, but read operation completion within single cycle becomes difficult
Solution Approach 1:
The centralized repair block acts as an intermediary that can buffer and manage data from long bitline structures. By introducing this intermediate stage with its own timing and control logic, the system can accommodate longer bitline discharge times while still meeting single-cycle throughput requirements through coordinated multiplexing
Data Source
AI summary
Embodiments provide centralized redundancy block repair for memory circuits. Certain embodiments are implemented in context of high-performance memory, such as last-level cache design, where the primary memory bank often uses high-density memory cells (“bitcells”) and supports long self-bitline structures to increase compactness. In such contexts, it can be difficult to finish read operations within a single cycle, even when the entire cache is divided into small bank pieces. Bank-interleaved structure in clusters can be implemented to allow access to different memory banks in consecutive cycles, thereby achieving overall single circle throughput (i.e., the latency can be masked by the interleaving). Accordingly, some embodiments of the centralized block repair can support bank interleaved access, for example, with a strict single-cycle throughput. Some embodiments can also support other features, such as row repair and/or column repair.