Centralized Power Gating Control for Low-Inrush IC Wake-Up
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Solution Overview
Problem
Integrated circuits face challenges in controlling inrush currents during power-up from shutdown or sleep modes, as existing power gating solutions either require significant area overhead or lack fine-grained control, leading to potential voltage droops and incorrect switching logic behavior.
Innovation Solution
A centralized power gating control circuit using trigger circuits to sequence the on/off switching of power gates based on precise voltage levels, employing a multi-level power gate architecture with Schmitt triggers to minimize inrush currents and ensure all power gates are turned on before enabling regular operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating circuits are used to reduce leakage power, then power consumption is reduced, but inrush currents occur during power-up from shutdown or sleep modes
Solution Approach 1:
The power gate is divided into multiple levels (first level, second level, third level) with each level controlled by separate trigger circuits. This segmentation allows gradual power-up sequencing where lower levels activate first, charging capacitance incrementally, thereby reducing peak inrush current while maintaining the power gating function for leakage reduction.
Solution Approach 2:
The trigger circuits are designed to activate power gate levels in a predetermined sequence before full operation is needed. The first trigger circuit activates the first level power gate preliminarily, which charges the capacitance in advance, preparing the system for subsequent level activation and preventing sudden inrush current when full power is required.
2Adaptability or versatility
If existing power gating solutions are used, then power management is achieved, but significant area overhead is required
Solution Approach 1:
Multiple trigger circuits are merged into a single centralized power gating control circuit that sequences the activation of multiple power gate levels. This consolidation reduces the total area overhead compared to having separate control circuits for each power gate, while maintaining fine-grained control over the power-up sequence and enabling versatile power management across different operational modes.
3Productivity
If power gates are turned on quickly, then productivity is improved, but voltage droops occur and switching logic behavior becomes incorrect
Solution Approach 1:
The power gate activation is performed in periodic stages through the multi-level architecture. Each trigger circuit activates its associated power gate level at a predetermined time in the sequence, creating a staged periodic action that balances speed with reliability. This ensures voltage stability during transitions and prevents incorrect switching logic behavior while maintaining acceptable power-up speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes area overhead, provides fine-grained control over inrush currents, and prevents voltage droops by ensuring all power gates are turned on before enabling regular operation, ensuring correct switching logic behavior and efficient power management.
Implementation Method 1
employing a multi-level power gate architecture with Schmitt triggers to minimize inrush currents
Data Source
AI summary
Power gating control and related circuitry for integrated circuits is described herein. A centralized power gating control circuit uses trigger circuits to control the on/off switching of power gating circuits distributed at different points in a chip, integrated circuit, module or block (collectively “IC”). The power gating circuits may include power gates partitioned for sleep and shutdown modes. The shutdown mode power gates may employ multi-level power gate architecture to minimize inrush current during power-up of the IC. Each level may be associated with or tied to a trigger circuit and activated based on a voltage level reaching the voltage threshold of the trigger circuit. The power gating control and related circuitry may be embedded in the IC.