Centralized Power Meter for Signal Processing Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The distributed arrangement of power meters in digital signal processing circuits leads to significant resource consumption and increased size, as multiple power meters are required for each power trace point, resulting in inefficient resource utilization and waste, especially since not all power meters are active at all times.
Innovation Solution
A centralized power meter and calculation method are introduced, where multiple sample buffers route requests to a shared power calculation core, utilizing a Quality of Service (QoS) scheduler to prioritize and manage power calculation tasks, allowing for flexible load balancing and efficient resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If distributed power meters are deployed at each power trace point, then power metering coverage is improved, but resource consumption and device size increase significantly
Solution Approach 1:
Multiple power metering requests from different sample buffers are merged and routed to a shared power calculation core through a switch. This consolidation allows a single computational resource to serve multiple metering functions, dramatically reducing overall resource consumption while maintaining comprehensive power monitoring coverage across all trace points.
Solution Approach 2:
The shared power calculation core is designed to handle multiple types of power metering requests simultaneously, serving as a universal computing resource for different sample buffers. This multi-functional approach replaces the need for dedicated power calculation cores at each trace point, reducing device size and resource usage while preserving metering capabilities.
2Productivity
If multiple power calculation cores are allocated to different sample buffers, then power calculation speed is improved, but resource consumption increases
Solution Approach 1:
The shared power calculation core continuously processes power metering requests from multiple sample buffers in sequence, maintaining continuous useful action without idle periods. The QoS scheduler ensures that the core is always engaged in meaningful computation, optimizing resource utilization and maintaining high productivity with a single core rather than requiring multiple cores to achieve the same throughput.
Solution Approach 2:
The system dynamically allocates the shared power calculation core to different sample buffers based on real-time priorities and workload demands. The QoS scheduler adjusts the assignment of the computing resource dynamically, allowing the single core to adaptively serve different metering functions with varying urgency, thereby maintaining high calculation speed without requiring static allocation of multiple cores.
3Use of energy by moving object
If a shared power calculation core is used for multiple sample buffers, then resource consumption is reduced, but access priority management becomes complex
Solution Approach 1:
A QoS (Quality of Service) scheduler is introduced as an intermediary component between multiple sample buffers and the shared power calculation core. This mediator manages access priorities, arbitration, and scheduling, handling the complexity of resource allocation centrally. By placing the scheduling logic in a dedicated intermediary module, the system reduces overall complexity compared to distributed priority management, while enabling fine-grained control over resource access.
4Productivity
If power calculation requests are processed in parallel, then calculation throughput is improved, but resource allocation efficiency decreases
Solution Approach 1:
The QoS scheduler implements periodic scheduling of power calculation requests from different sample buffers, creating a structured rhythm of resource allocation. Instead of chaotic parallel processing that wastes resources on context switching and coordination overhead, the system uses periodic time-sliced access patterns that maintain high throughput while optimizing resource allocation efficiency. This periodic structure allows the single core to systematically serve multiple buffers with minimal idle time.
Data Source
AI summary
The present disclosure provides a centralized power meter for a signal processing circuit, comprising: M sample buffers, each configured to buffer samples respectively from at least one of N sources, and trigger a request for power calculation of the buffered samples in response to the buffered samples, the request having a corresponding priority; a switch, configured to route the requests from the M sample buffers to one or more power calculation cores; the one or more power calculation cores, each configured to retrieve the samples from the sample buffer in an order of their corresponding priorities, in response to the routed requests, and to perform power calculation of the retrieved samples, wherein N and M are integers no less than 1, and N is no less than M. The present disclosure further provides a centralized power calculation method.