Centralized SRAM ECC Module for Double-Bit Error Correction
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Solution Overview
Problem
Current data storage devices, such as solid state drives (SSDs), face limitations in double-error-correction capabilities, leading to reduced storage space and increased decoding time due to the need for additional redundant bits, which can hinder operational frequency.
Innovation Solution
Implementing a data storage device with two or more memory devices and a controller that programs additional error correction code (ECC) to a distinct central module, enabling enhanced decoding capabilities for accurate double-error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If other ECC codewords with double-error-correction capability are used to provide accurate position of two bit flips, then error correction capability is improved, but more redundant bits are required which increases ECC codeword size
Solution Approach 1:
The patent divides the ECC system into two segments: a first ECC codeword with basic error correction capability and a second ECC codeword with double-error-correction capability. This segmentation allows the system to achieve accurate double-error correction while using only a portion of the total codeword for the more resource-intensive double-error-correction function, thereby reducing the overall redundant bit requirement compared to using a full double-error-correction codeword for all data.
2Measurement precision
If other ECC codewords with double-error-correction capability are used, then accurate position of two bit flips can be provided, but decoding time is increased
Solution Approach 1:
The patent applies partial action by using the second ECC codeword with double-error-correction capability only when needed (i.e., when double-bit errors are detected or suspected), rather than always using it for every decoding operation. This allows the system to maintain high measurement precision for error position detection when required, while avoiding the constant time penalty of using the more complex decoding algorithm for all operations.
3Reliability
If additional redundant bits are added to increase ECC codeword size for double-error-correction, then error correction capability is improved, but maximum operational frequency is reduced
Solution Approach 1:
The patent implements a dynamic ECC system where the decoding complexity and operational characteristics can adapt based on error conditions. The system selectively applies the second ECC codeword with double-error-correction capability only when double-bit errors are detected, allowing the operational frequency to remain high during normal operation while providing enhanced error correction capability when needed. This dynamic approach prevents the continuous performance penalty associated with always using the more complex decoding algorithm.
Data Source
AI summary
A data storage device includes two or more memory devices and a controller coupled to the two or more memory devices. The controller is configured to program data to one or more memory devices of the two or more memory devices, select one or more of the one or more memory devices to have additional ECC for the data of the one or more memory devices, program the additional ECC to a first memory device. The data is programmed with error correction code (ECC). The first memory device is distinct from the one or more memory devices. The first memory device is disposed in a central module, where the central module includes additional decoding capability. The additional ECC and the corresponding data with ECC are concatenated and decoded for additional error correction capability.